[Bug target/109104] New: [13 Regression] ICE: in gen_reg_rtx, at emit-rtl.cc:1171 with -fzero-call-used-regs=all -march=rv64gv

[Bug target/109104] New: [13 Regression] ICE: in gen_reg_rtx, at emit-rtl.cc:1171 with -fzero-call-used-regs=all -march=rv64gv

[zsojka at seznam dot cz]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109104

            Bug ID: 109104
           Summary: [13 Regression] ICE: in gen_reg_rtx, at
                    emit-rtl.cc:1171 with -fzero-call-used-regs=all
                    -march=rv64gv
           Product: gcc
           Version: 13.0
            Status: UNCONFIRMED
          Keywords: ice-on-valid-code
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: zsojka at seznam dot cz
  Target Milestone: ---
              Host: x86_64-pc-linux-gnu
            Target: riscv64-unknown-linux-gnu

Compiler output:
$ cat testcase.c 
void foo(void) {}
$ riscv64-unknown-linux-gnu-gcc -fzero-call-used-regs=all -march=rv64gv
testcase.c 
during RTL pass: zero_call_used_regs
testcase.c: In function 'foo':
testcase.c:1:17: internal compiler error: in gen_reg_rtx, at emit-rtl.cc:1171
    1 | void foo(void) {}
      |                 ^
0x6f9f83 gen_reg_rtx(machine_mode)
        /repo/gcc-trunk/gcc/emit-rtl.cc:1171
0x14ca5d4 emit_vlmax_vsetvl
        /repo/gcc-trunk/gcc/config/riscv/riscv-v.cc:115
0x14ca5d4 emit_pred_op
        /repo/gcc-trunk/gcc/config/riscv/riscv-v.cc:189
0x14ca9e1 riscv_vector::emit_vlmax_op(unsigned int, rtx_def*, rtx_def*,
machine_mode)
        /repo/gcc-trunk/gcc/config/riscv/riscv-v.cc:207
0x14ca9e1 expand_const_vector
        /repo/gcc-trunk/gcc/config/riscv/riscv-v.cc:239
0x14ca9e1 riscv_vector::legitimize_move(rtx_def*, rtx_def*, machine_mode)
        /repo/gcc-trunk/gcc/config/riscv/riscv-v.cc:265
0x19c9500 gen_movvnx2qi(rtx_def*, rtx_def*)
        /repo/gcc-trunk/gcc/config/riscv/vector.md:563
0xcbe9f1 rtx_insn* insn_gen_fn::operator()<rtx_def*, rtx_def*>(rtx_def*,
rtx_def*) const
        /repo/gcc-trunk/gcc/recog.h:407
0xcbe9f1 emit_move_insn_1(rtx_def*, rtx_def*)
        /repo/gcc-trunk/gcc/expr.cc:4172
0xcbee1f emit_move_insn(rtx_def*, rtx_def*)
        /repo/gcc-trunk/gcc/expr.cc:4342
0x109b93b default_zero_call_used_regs(HARD_REG_SET)
        /repo/gcc-trunk/gcc/targhooks.cc:1094
0xd1e4aa gen_call_used_regs_seq
        /repo/gcc-trunk/gcc/function.cc:5950
0xd1e4aa execute
        /repo/gcc-trunk/gcc/function.cc:6744
Please submit a full bug report, with preprocessed source (by using
-freport-bug).
Please include the complete backtrace with any bug report.
See <https://gcc.gnu.org/bugs/> for instructions.

$ riscv64-unknown-linux-gnu-gcc -v
Using built-in specs.
COLLECT_GCC=/repo/gcc-trunk/binary-latest-riscv64/bin/riscv64-unknown-linux-gnu-gcc
COLLECT_LTO_WRAPPER=/repo/gcc-trunk/binary-trunk-r13-6502-20230306110826-gb83acefb040-checking-yes-rtl-df-extra-riscv64/bin/../libexec/gcc/riscv64-unknown-linux-gnu/13.0.1/lto-wrapper
Target: riscv64-unknown-linux-gnu
Configured with: /repo/gcc-trunk//configure --enable-languages=c,c++
--enable-valgrind-annotations --disable-nls --enable-checking=yes,rtl,df,extra
--with-cloog --with-ppl --with-isl --with-isa-spec=2.2
--with-sysroot=/usr/riscv64-unknown-linux-gnu --build=x86_64-pc-linux-gnu
--host=x86_64-pc-linux-gnu --target=riscv64-unknown-linux-gnu
--with-ld=/usr/bin/riscv64-unknown-linux-gnu-ld
--with-as=/usr/bin/riscv64-unknown-linux-gnu-as --disable-multilib
--disable-libstdcxx-pch
--prefix=/repo/gcc-trunk//binary-trunk-r13-6502-20230306110826-gb83acefb040-checking-yes-rtl-df-extra-riscv64
Thread model: posix
Supported LTO compression algorithms: zlib zstd
gcc version 13.0.1 20230306 (experimental) (GCC)

[Bug target/109104] [13 Regression] ICE: in gen_reg_rtx, at emit-rtl.cc:1171 with -fzero-call-used-regs=all -march=rv64gv

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109104

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Target Milestone|---                         |13.0

[Bug target/109104] [13 Regression] ICE: in gen_reg_rtx, at emit-rtl.cc:1171 with -fzero-call-used-regs=all -march=rv64gv

[roger at nextmovesoftware dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109104

Roger Sayle <roger at nextmovesoftware dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |roger at nextmovesoftware dot com

--- Comment #1 from Roger Sayle <roger at nextmovesoftware dot com> ---
Not exactly my area of expertise, but adding

  if (!can_create_pseudo_p ())
    return false;

at the start of legitimize_move on line 262 of riscv-v.cc should help.
Other solutions include clearing a vector register without requiring
a scalar register (to set the vector length) by xoring it with itself,
or possibly providing a riscv backend target hook to override the default
default_zero_call_used_regs implementation.

If the vector length can be set to zero, that might be an alternative
to clearing call-used vector registers.

[Bug target/109104] [13 Regression] ICE: in gen_reg_rtx, at emit-rtl.cc:1171 with -fzero-call-used-regs=all -march=rv64gv

[juzhe.zhong at rivai dot ai]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109104

--- Comment #2 from JuzheZhong <juzhe.zhong at rivai dot ai> ---
(In reply to Roger Sayle from comment #1)
> Not exactly my area of expertise, but adding
> 
>   if (!can_create_pseudo_p ())
>     return false;
> 
> at the start of legitimize_move on line 262 of riscv-v.cc should help.
> Other solutions include clearing a vector register without requiring
> a scalar register (to set the vector length) by xoring it with itself,
> or possibly providing a riscv backend target hook to override the default
> default_zero_call_used_regs implementation.
> 
> If the vector length can be set to zero, that might be an alternative
> to clearing call-used vector registers.

We (me && kito) are trying to find the solution to fix it.
Actually, xoring itself can not help since vxor.vv also needs 
vsetvl a5,zero.... Setting vector-length to be VLMAX.

We don't have an instruction in RVV ISA can zero a whole vector register
without
vsetvl to setting VLMAX vector-length.

I think maybe Kito knows how to fix it.

We will definetely fix it soon in GCC 13.

Thanks.

[Bug target/109104] [13 Regression] ICE: in gen_reg_rtx, at emit-rtl.cc:1171 with -fzero-call-used-regs=all -march=rv64gv

[marxin at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109104

Martin Liška <marxin at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Keywords|needs-bisection             |
   Last reconfirmed|                            |2023-03-30
             Status|UNCONFIRMED                 |NEW
     Ever confirmed|0                           |1
                 CC|                            |marxin at gcc dot gnu.org

--- Comment #3 from Martin Liška <marxin at gcc dot gnu.org> ---
Started with r13-2819-gb4feb49cf308b3, it was rejected before the revision
with:
<stdin>:1:17: sorry, unimplemented: argument ‘all’ is not supported for
‘-fzero-call-used-regs’ on this target

[Bug target/109104] [13 Regression] ICE: in gen_reg_rtx, at emit-rtl.cc:1171 with -fzero-call-used-regs=all -march=rv64gv

[kito at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109104

Kito Cheng <kito at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|NEW                         |ASSIGNED
                 CC|                            |kito at gcc dot gnu.org
           Assignee|unassigned at gcc dot gnu.org      |pan2.li at intel dot com

--- Comment #4 from Kito Cheng <kito at gcc dot gnu.org> ---
Pan Li from Intel is working on fixing that

[Bug target/109104] [13 Regression] ICE: in gen_reg_rtx, at emit-rtl.cc:1171 with -fzero-call-used-regs=all -march=rv64gv

[yanzhang.wang at intel dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109104

Yanzhang, Wang <yanzhang.wang at intel dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |yanzhang.wang at intel dot com

--- Comment #5 from Yanzhang, Wang <yanzhang.wang at intel dot com> ---
We are still working on it. Hope it can be pushed soon.

[Bug target/109104] [13 Regression] ICE: in gen_reg_rtx, at emit-rtl.cc:1171 with -fzero-call-used-regs=all -march=rv64gv

[law at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109104

Jeffrey A. Law <law at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |law at gcc dot gnu.org
           Priority|P3                          |P4

[Bug target/109104] [13 Regression] ICE: in gen_reg_rtx, at emit-rtl.cc:1171 with -fzero-call-used-regs=all -march=rv64gv

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109104

--- Comment #6 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Kito Cheng <kito@gcc.gnu.org>:

https://gcc.gnu.org/g:40fc8e3d4f600d89e6b065d6f12db7a816269c8f

commit r13-7138-g40fc8e3d4f600d89e6b065d6f12db7a816269c8f
Author: Yanzhang Wang <yanzhang.wang@intel.com>
Date:   Tue Apr 11 19:37:48 2023 +0800

    RISC-V: Fix regression of -fzero-call-used-regs=all [PR109104]

    This patch registers a riscv specific function to
    TARGET_ZERO_CALL_USED_REGS instead of default in targhooks.cc. It will
    clean gpr and vector relevant registers.

    gcc/ChangeLog:

            PR target/109104
            * config/riscv/riscv-protos.h (emit_hard_vlmax_vsetvl): New.
            * config/riscv/riscv-v.cc (emit_hard_vlmax_vsetvl): New.
            (emit_vlmax_vsetvl): Use emit_hard_vlmax_vsetvl.
            * config/riscv/riscv.cc (vector_zero_call_used_regs): New.
            (riscv_zero_call_used_regs): New.
            (TARGET_ZERO_CALL_USED_REGS): New.

    gcc/testsuite/ChangeLog:

            PR target/109104
            * gcc.target/riscv/zero-scratch-regs-1.c: New test.
            * gcc.target/riscv/zero-scratch-regs-2.c: New test.
            * gcc.target/riscv/zero-scratch-regs-3.c: New test.

    Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com>
    Co-authored-by: Pan Li <pan2.li@intel.com>
    Co-authored-by: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
    Co-authored-by: Kito Cheng <kito.cheng@sifive.com>

[Bug target/109104] [13/14 Regression] ICE: in gen_reg_rtx, at emit-rtl.cc:1171 with -fzero-call-used-regs=all -march=rv64gv

[kito at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109104

Kito Cheng <kito at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|ASSIGNED                    |RESOLVED
         Resolution|---                         |FIXED

--- Comment #7 from Kito Cheng <kito at gcc dot gnu.org> ---
Fixed on trunk