* [Bug target/109977] [14 Regression] ICE: output_operand: incompatible floating point / vector register operand for '%d' at -Og
2023-05-26 5:14 [Bug target/109977] New: [14 Regression] ICE: output_operand: incompatible floating point / vector register operand for '%d' at -Og zsojka at seznam dot cz
@ 2023-05-26 5:30 ` pinskia at gcc dot gnu.org
2023-05-26 5:31 ` pinskia at gcc dot gnu.org
` (6 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: pinskia at gcc dot gnu.org @ 2023-05-26 5:30 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109977
Andrew Pinski <pinskia at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Target Milestone|--- |14.0
Host|x86_64-pc-linux-gnu |
Last reconfirmed| |2023-05-26
Ever confirmed|0 |1
Status|UNCONFIRMED |NEW
--- Comment #1 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
(insn 12 11 13 (set (mem/c:V2DF (plus:DI (reg/f:DI 31 sp)
(const_int 16 [0x10])) [1 w+0 S16 A128])
(vec_duplicate:V2DF (reg:DF 0 x0 [orig:95 v ] [95])))
"/app/example.cpp":12:5 1392 {aarch64_simd_stpv2df}
(expr_list:REG_DEAD (reg:DF 0 x0 [orig:95 v ] [95])
(nil)))
(define_insn "aarch64_simd_stp<mode>"
[(set (match_operand:VP_2E 0 "aarch64_mem_pair_lanes_operand" "=Umn,Umn")
(vec_duplicate:VP_2E (match_operand:<VEL> 1 "register_operand"
"w,r")))]
"TARGET_SIMD"
"@
stp\\t%<Vetype>1, %<Vetype>1, %y0
stp\\t%<vw>1, %<vw>1, %y0"
[(set_attr "type" "neon_stp, store_<ldpstp_vel_sz>")]
)
;; For scalar usage of vector/FP registers, widening
(define_mode_attr vw [(V8QI "w") (V16QI "w")
(V4HI "w") (V8HI "w")
(V2SI "w") (V4SI "w")
(DI "x") (V2DI "x")
(V2SF "s") (V4SF "s")
(V2DF "d")])
Most likely should be using vwcore instead:
;; Corresponding core element mode for each vector mode. This is a
;; variation on <vw> mapping FP modes to GP regs.
(define_mode_attr vwcore [(V8QI "w") (V16QI "w")
(V4HI "w") (V8HI "w")
(V2SI "w") (V4SI "w")
(DI "x") (V2DI "x")
(V4HF "w") (V8HF "w")
(V4BF "w") (V8BF "w")
(V2SF "w") (V4SF "w")
(V2DF "x")
(VNx16QI "w") (VNx8QI "w") (VNx4QI "w") (VNx2QI "w")
(VNx8HI "w") (VNx4HI "w") (VNx2HI "w")
(VNx8HF "w") (VNx4HF "w") (VNx2HF "w")
(VNx8BF "w") (VNx4BF "w") (VNx2BF "w")
(VNx4SI "w") (VNx2SI "w")
(VNx4SF "w") (VNx2SF "w")
(VNx2DI "x")
(VNx2DF "x")])
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Bug target/109977] [14 Regression] ICE: output_operand: incompatible floating point / vector register operand for '%d' at -Og
2023-05-26 5:14 [Bug target/109977] New: [14 Regression] ICE: output_operand: incompatible floating point / vector register operand for '%d' at -Og zsojka at seznam dot cz
2023-05-26 5:30 ` [Bug target/109977] " pinskia at gcc dot gnu.org
@ 2023-05-26 5:31 ` pinskia at gcc dot gnu.org
2023-08-02 20:48 ` pinskia at gcc dot gnu.org
` (5 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: pinskia at gcc dot gnu.org @ 2023-05-26 5:31 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109977
--- Comment #2 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Introduced by r14-215-g85279b0bddc1c5 .
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Bug target/109977] [14 Regression] ICE: output_operand: incompatible floating point / vector register operand for '%d' at -Og
2023-05-26 5:14 [Bug target/109977] New: [14 Regression] ICE: output_operand: incompatible floating point / vector register operand for '%d' at -Og zsojka at seznam dot cz
2023-05-26 5:30 ` [Bug target/109977] " pinskia at gcc dot gnu.org
2023-05-26 5:31 ` pinskia at gcc dot gnu.org
@ 2023-08-02 20:48 ` pinskia at gcc dot gnu.org
2023-10-17 10:35 ` rguenth at gcc dot gnu.org
` (4 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: pinskia at gcc dot gnu.org @ 2023-08-02 20:48 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109977
Andrew Pinski <pinskia at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
CC| |slyfox at gcc dot gnu.org
--- Comment #3 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
*** Bug 110880 has been marked as a duplicate of this bug. ***
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Bug target/109977] [14 Regression] ICE: output_operand: incompatible floating point / vector register operand for '%d' at -Og
2023-05-26 5:14 [Bug target/109977] New: [14 Regression] ICE: output_operand: incompatible floating point / vector register operand for '%d' at -Og zsojka at seznam dot cz
` (2 preceding siblings ...)
2023-08-02 20:48 ` pinskia at gcc dot gnu.org
@ 2023-10-17 10:35 ` rguenth at gcc dot gnu.org
2023-11-24 11:59 ` jakub at gcc dot gnu.org
` (3 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: rguenth at gcc dot gnu.org @ 2023-10-17 10:35 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109977
Richard Biener <rguenth at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Priority|P3 |P1
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Bug target/109977] [14 Regression] ICE: output_operand: incompatible floating point / vector register operand for '%d' at -Og
2023-05-26 5:14 [Bug target/109977] New: [14 Regression] ICE: output_operand: incompatible floating point / vector register operand for '%d' at -Og zsojka at seznam dot cz
` (3 preceding siblings ...)
2023-10-17 10:35 ` rguenth at gcc dot gnu.org
@ 2023-11-24 11:59 ` jakub at gcc dot gnu.org
2023-11-24 12:03 ` [Bug target/109977] [14 Regression] ICE: output_operand: incompatible floating point / vector register operand for '%d' at -Og since r14-215-g85279b0bddc1c5 sjames at gcc dot gnu.org
` (2 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: jakub at gcc dot gnu.org @ 2023-11-24 11:59 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109977
Jakub Jelinek <jakub at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
CC| |jakub at gcc dot gnu.org
--- Comment #4 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
I agree with the analysis and
2023-11-24 Andrew Pinski <pinskia@gmail.com>
Jakub Jelinek <jakub@redhat.com>
* config/aarch64/aarch64-simd.md (aarch64_simd_stp<mode>): Use <vwcore>
rather than %<vw> for alternative with r constraint on input operand.
* gcc.dg/pr109977.c: New test.
--- gcc/config/aarch64/aarch64-simd.md.jj 2023-11-22 22:55:20.577075762
+0100
+++ gcc/config/aarch64/aarch64-simd.md 2023-11-24 12:51:22.855215700 +0100
@@ -269,7 +269,7 @@ (define_insn "aarch64_simd_stp<mode>"
"TARGET_SIMD"
{@ [ cons: =0 , 1 ; attrs: type ]
[ Umn , w ; neon_stp ] stp\t%<Vetype>1, %<Vetype>1,
%y0
- [ Umn , r ; store_<ldpstp_vel_sz> ] stp\t%<vw>1, %<vw>1, %y0
+ [ Umn , r ; store_<ldpstp_vel_sz> ] stp\t%<vwcore>1, %<vwcore>1,
%y0
}
)
--- gcc/testsuite/gcc.dg/pr109977.c.jj 2023-11-24 12:51:04.551473591 +0100
+++ gcc/testsuite/gcc.dg/pr109977.c 2023-11-24 12:50:44.158760916 +0100
@@ -0,0 +1,16 @@
+/* PR target/109977 */
+/* { dg-do compile } */
+/* { dg-options "-Og" } */
+
+typedef double __attribute__((__vector_size__ (8))) V;
+typedef double __attribute__((__vector_size__ (16))) W;
+V v;
+int i;
+extern void bar (void *);
+
+void
+foo (void)
+{
+ W w = __builtin_shufflevector (v, (W) { }, 0, 0);
+ bar (&w);
+}
fixes it (though it will take me a while to find where to bootstrap/regtest
this).
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Bug target/109977] [14 Regression] ICE: output_operand: incompatible floating point / vector register operand for '%d' at -Og since r14-215-g85279b0bddc1c5
2023-05-26 5:14 [Bug target/109977] New: [14 Regression] ICE: output_operand: incompatible floating point / vector register operand for '%d' at -Og zsojka at seznam dot cz
` (4 preceding siblings ...)
2023-11-24 11:59 ` jakub at gcc dot gnu.org
@ 2023-11-24 12:03 ` sjames at gcc dot gnu.org
2023-11-25 9:31 ` cvs-commit at gcc dot gnu.org
2023-11-25 9:33 ` jakub at gcc dot gnu.org
7 siblings, 0 replies; 9+ messages in thread
From: sjames at gcc dot gnu.org @ 2023-11-24 12:03 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109977
--- Comment #5 from Sam James <sjames at gcc dot gnu.org> ---
If needed, you can email me an SSH key for a Neoverse-N1 (fp asimd evtstrm aes
pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp
ssbs) which should be fast.
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Bug target/109977] [14 Regression] ICE: output_operand: incompatible floating point / vector register operand for '%d' at -Og since r14-215-g85279b0bddc1c5
2023-05-26 5:14 [Bug target/109977] New: [14 Regression] ICE: output_operand: incompatible floating point / vector register operand for '%d' at -Og zsojka at seznam dot cz
` (5 preceding siblings ...)
2023-11-24 12:03 ` [Bug target/109977] [14 Regression] ICE: output_operand: incompatible floating point / vector register operand for '%d' at -Og since r14-215-g85279b0bddc1c5 sjames at gcc dot gnu.org
@ 2023-11-25 9:31 ` cvs-commit at gcc dot gnu.org
2023-11-25 9:33 ` jakub at gcc dot gnu.org
7 siblings, 0 replies; 9+ messages in thread
From: cvs-commit at gcc dot gnu.org @ 2023-11-25 9:31 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109977
--- Comment #6 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Jakub Jelinek <jakub@gcc.gnu.org>:
https://gcc.gnu.org/g:a6a43a3b763816fec7c4eec6ae7be5b263dff340
commit r14-5840-ga6a43a3b763816fec7c4eec6ae7be5b263dff340
Author: Jakub Jelinek <jakub@redhat.com>
Date: Sat Nov 25 10:30:39 2023 +0100
aarch64: Fix up aarch64_simd_stp<mode> [PR109977]
The aarch64_simd_stp<mode> pattern uses w constraint in one alternative and
r in another, but for the latter incorrectly uses <vw> iterator in %<vw>1
which
expands to %d1 for V2DF and %s1 for V2SF and V4SF (this one not relevant to
the pattern) and %w1 for others, so it ICEs if the alternative is selected
during final. Compared to this, <vwcore> macro has the same values for all
modes but uses w for V2DF and V2SF.
2023-11-24 Andrew Pinski <pinskia@gmail.com>
Jakub Jelinek <jakub@redhat.com>
PR target/109977
* config/aarch64/aarch64-simd.md (aarch64_simd_stp<mode>): Use
<vwcore>
rather than %<vw> for alternative with r constraint on input
operand.
* gcc.dg/pr109977.c: New test.
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Bug target/109977] [14 Regression] ICE: output_operand: incompatible floating point / vector register operand for '%d' at -Og since r14-215-g85279b0bddc1c5
2023-05-26 5:14 [Bug target/109977] New: [14 Regression] ICE: output_operand: incompatible floating point / vector register operand for '%d' at -Og zsojka at seznam dot cz
` (6 preceding siblings ...)
2023-11-25 9:31 ` cvs-commit at gcc dot gnu.org
@ 2023-11-25 9:33 ` jakub at gcc dot gnu.org
7 siblings, 0 replies; 9+ messages in thread
From: jakub at gcc dot gnu.org @ 2023-11-25 9:33 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109977
Jakub Jelinek <jakub at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Resolution|--- |FIXED
Status|NEW |RESOLVED
--- Comment #7 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
Fixed.
^ permalink raw reply [flat|nested] 9+ messages in thread