[Bug c/110265] New: RISC-V: ICE when build RVV intrinsic with "-march=rv32gc_zve64d -mabi=ilp32d"

["pan2.li at intel dot com" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110265

            Bug ID: 110265
           Summary: RISC-V: ICE when build RVV intrinsic with
                    "-march=rv32gc_zve64d -mabi=ilp32d"
           Product: gcc
           Version: 14.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: c
          Assignee: unassigned at gcc dot gnu.org
          Reporter: pan2.li at intel dot com
  Target Milestone: ---

Created attachment 55325
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=55325&action=edit
Reproduce source code

Given we have the below code.

#include "riscv_vector.h"

vint16m1_t test_vredmax_vs_i16mf4_i16m1(vint16mf4_t vector, vint16m1_t scalar,
size_t vl) {
  return __riscv_vredmax_vs_i16mf4_i16m1(vector, scalar, vl);
}

There will be the ICE when build similar as "riscv64-unknown-elf-gcc
-march=rv32gc_zve64d -mabi=ilp32d -O3 -Wno-psabi test-int.c  -c -S -o -".

>> ../__RISC-V_INSTALL_/bin/riscv64-unknown-elf-gcc -march=rv32gc_zve64d -mabi=ilp32d -O3 -Wno-psabi test-int.c  -c -S -o -
        .file   "test-int.c"
        .option nopic
        .attribute arch,
"rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
        .attribute unaligned_access, 0
        .attribute stack_align, 16
        .text
test-int.c: In function ‘test_vredmax_vs_i16mf4_i16m1’:
test-int.c:4:10: error: invalid argument to built-in function
    4 |   return __riscv_vredmax_vs_i16mf4_i16m1(vector, scalar, vl);
      |          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
during RTL pass: expand
test-int.c:4:10: internal compiler error: Segmentation fault
0x16e7017 crash_signal
       
/home/pli/repos/gcc/333/riscv-gnu-toolchain/gcc/__RISC-V_BUILD/../gcc/toplev.cc:314
0x7f9dcf04251f ???
        ./signal/../sysdeps/unix/sysv/linux/x86_64/libc_sigaction.c:0
0x111b9fa store_expr(tree_node*, rtx_def*, int, bool, bool)
       
/home/pli/repos/gcc/333/riscv-gnu-toolchain/gcc/__RISC-V_BUILD/../gcc/expr.cc:6352
0x1119e77 expand_assignment(tree_node*, tree_node*, bool)
       
/home/pli/repos/gcc/333/riscv-gnu-toolchain/gcc/__RISC-V_BUILD/../gcc/expr.cc:6048
0xf64d2c expand_call_stmt
       
/home/pli/repos/gcc/333/riscv-gnu-toolchain/gcc/__RISC-V_BUILD/../gcc/cfgexpand.cc:2829
0xf68ac6 expand_gimple_stmt_1
       
/home/pli/repos/gcc/333/riscv-gnu-toolchain/gcc/__RISC-V_BUILD/../gcc/cfgexpand.cc:3880
0xf691b3 expand_gimple_stmt
       
/home/pli/repos/gcc/333/riscv-gnu-toolchain/gcc/__RISC-V_BUILD/../gcc/cfgexpand.cc:4044
0xf71d20 expand_gimple_basic_block
       
/home/pli/repos/gcc/333/riscv-gnu-toolchain/gcc/__RISC-V_BUILD/../gcc/cfgexpand.cc:6096
0xf74279 execute
       
/home/pli/repos/gcc/333/riscv-gnu-toolchain/gcc/__RISC-V_BUILD/../gcc/cfgexpand.cc:6831