[Bug c/110265] RISC-V: ICE when build RVV intrinsic integer reduction with "-march=rv32gc_zve64d -mabi=ilp32d", both GCC 14 and 13.

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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110265

--- Comment #2 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Pan Li <panli@gcc.gnu.org>:

https://gcc.gnu.org/g:d0cf0c6c8449009697ad29dd7cb60e7f655628f2

commit r14-1899-gd0cf0c6c8449009697ad29dd7cb60e7f655628f2
Author: Pan Li <pan2.li@intel.com>
Date:   Fri Jun 16 15:01:46 2023 +0800

    RISC-V: Bugfix for RVV integer reduction in ZVE32/64.

    The rvv integer reduction has 3 different patterns for zve128+, zve64
    and zve32. They take the same iterator with different attributions.
    However, we need the generated function code_for_reduc (code, mode1,
mode2).
    The implementation of code_for_reduc may look like below.

    code_for_reduc (code, mode1, mode2)
    {
      if (code == max && mode1 == VNx1QI && mode2 == VNx1QI)
        return CODE_FOR_pred_reduc_maxvnx1qivnx16qi; // ZVE128+

      if (code == max && mode1 == VNx1QI && mode2 == VNx1QI)
        return CODE_FOR_pred_reduc_maxvnx1qivnx8qi;  // ZVE64

      if (code == max && mode1 == VNx1QI && mode2 == VNx1QI)
        return CODE_FOR_pred_reduc_maxvnx1qivnx4qi;  // ZVE32
    }

    Thus there will be a problem here. For example zve32, we will have
    code_for_reduc (max, VNx1QI, VNx1QI) which will return the code of
    the ZVE128+ instead of the ZVE32 logically.

    This patch will merge the 3 patterns into pattern, and pass both the
    input_vector and the ret_vector of code_for_reduc. For example, ZVE32 will
be
    code_for_reduc (max, VNx1Q1, VNx8QI), then the correct code of ZVE32
    will be returned as expectation.

    Please note both GCC 13 and 14 are impacted by this issue.

    Signed-off-by: Pan Li <pan2.li@intel.com>
    Co-Authored by: Juzhe-Zhong <juzhe.zhong@rivai.ai>

            PR target/110265

    gcc/ChangeLog:

            * config/riscv/riscv-vector-builtins-bases.cc: Add ret_mode for
            integer reduction expand.
            * config/riscv/vector-iterators.md: Add VQI, VHI, VSI and VDI,
            and the LMUL1 attr respectively.
            * config/riscv/vector.md
            (@pred_reduc_<reduc><mode><vlmul1>): Removed.
            (@pred_reduc_<reduc><mode><vlmul1_zve64>): Likewise.
            (@pred_reduc_<reduc><mode><vlmul1_zve32>): Likewise.
            (@pred_reduc_<reduc><VQI:mode><VQI_LMUL1:mode>): New pattern.
            (@pred_reduc_<reduc><VHI:mode><VHI_LMUL1:mode>): Likewise.
            (@pred_reduc_<reduc><VSI:mode><VSI_LMUL1:mode>): Likewise.
            (@pred_reduc_<reduc><VDI:mode><VDI_LMUL1:mode>): Likewise.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/base/pr110265-1.c: New test.
            * gcc.target/riscv/rvv/base/pr110265-1.h: New test.
            * gcc.target/riscv/rvv/base/pr110265-2.c: New test.
            * gcc.target/riscv/rvv/base/pr110265-2.h: New test.
            * gcc.target/riscv/rvv/base/pr110265-3.c: New test.