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From: "juzhe.zhong at rivai dot ai" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug c/110265] RISC-V: ICE when build RVV intrinsic with "-march=rv32gc_zve64d -mabi=ilp32d", both GCC 14 and 13.
Date: Thu, 15 Jun 2023 07:59:04 +0000 [thread overview]
Message-ID: <bug-110265-4-Wh8T25uV2b@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-110265-4@http.gcc.gnu.org/bugzilla/>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110265
--- Comment #1 from JuzheZhong <juzhe.zhong at rivai dot ai> ---
This issue is caused by incorrect redcution instructions:
(define_insn "@pred_reduc_<reduc><mode><vlmul1>"
[(set (match_operand:<VLMUL1> 0 "register_operand" "=vr, vr")
(unspec:<VLMUL1>
[(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
(match_operand 5 "vector_length_operand" " rK, rK")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(any_reduc:VI
(vec_duplicate:VI
(vec_select:<VEL>
(match_operand:<VLMUL1> 4 "register_operand" " vr, vr")
(parallel [(const_int 0)])))
(match_operand:VI 3 "register_operand" " vr, vr"))
(match_operand:<VLMUL1> 2 "vector_merge_operand" " vu, 0")]
UNSPEC_REDUC))]
"TARGET_VECTOR && TARGET_MIN_VLEN >= 128"
"vred<reduc>.vs\t%0,%3,%4%p1"
[(set_attr "type" "vired")
(set_attr "mode" "<MODE>")])
(define_insn "@pred_reduc_<reduc><mode><vlmul1_zve64>"
[(set (match_operand:<VLMUL1_ZVE64> 0 "register_operand" "=vr,
vr")
(unspec:<VLMUL1_ZVE64>
[(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
(match_operand 5 "vector_length_operand" " rK, rK")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(any_reduc:VI_ZVE64
(vec_duplicate:VI_ZVE64
(vec_select:<VEL>
(match_operand:<VLMUL1_ZVE64> 4 "register_operand" " vr,
vr")
(parallel [(const_int 0)])))
(match_operand:VI_ZVE64 3 "register_operand" " vr,
vr"))
(match_operand:<VLMUL1_ZVE64> 2 "vector_merge_operand" " vu,
0")] UNSPEC_REDUC))]
"TARGET_VECTOR && TARGET_MIN_VLEN == 64"
"vred<reduc>.vs\t%0,%3,%4%p1"
[(set_attr "type" "vired")
(set_attr "mode" "<MODE>")])
(define_insn "@pred_reduc_<reduc><mode><vlmul1_zve32>"
[(set (match_operand:<VLMUL1_ZVE32> 0 "register_operand" "=vd, vd,
vr, vr")
(unspec:<VLMUL1_ZVE32>
[(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm,
vm,Wc1,Wc1")
(match_operand 5 "vector_length_operand" " rK, rK,
rK, rK")
(match_operand 6 "const_int_operand" " i, i,
i, i")
(match_operand 7 "const_int_operand" " i, i,
i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(any_reduc:VI_ZVE32
(vec_duplicate:VI_ZVE32
(vec_select:<VEL>
(match_operand:<VLMUL1_ZVE32> 4 "register_operand" " vr, vr,
vr, vr")
(parallel [(const_int 0)])))
(match_operand:VI_ZVE32 3 "register_operand" " vr, vr,
vr, vr"))
(match_operand:<VLMUL1_ZVE32> 2 "vector_merge_operand" " vu, 0,
vu, 0")] UNSPEC_REDUC))]
"TARGET_VECTOR && TARGET_MIN_VLEN == 32"
"vred<reduc>.vs\t%0,%3,%4%p1"
[(set_attr "type" "vired")
(set_attr "mode" "<MODE>")])
This 3 patterns are using same iterators, but different attributes.
For example, for VNx1QI reduction.
The first pattern is pred_reduc_sumvnx1qivnx16qi (since vnx16qi is the LMUL =
1mode for TARGET_MIN_VLEN >= 128).
The first pattern is pred_reduc_sumvnx1qivnx8qi (since vnx8qi is the LMUL =
1mode for TARGET_MIN_VLEN == 64).
The first pattern is pred_reduc_sumvnx1qivnx4qi (since vnx4qi is the LMUL =
1mode for TARGET_MIN_VLEN == 32).
Even though their patterns name are different, but share same iterators same
code_for
They are all using code_for_reduc (UNSPEC, vnx1qi).
We can't differentiate them.
So the idea should be merge them into same pattern:
(define_mode_iterator VQI [
(VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI VNx4QI VNx8QI VNx16QI VNx32QI
(VNx64QI "TARGET_MIN_VLEN > 32") (VNx128QI "TARGET_MIN_VLEN >= 128")
])
(define_mode_iterator VQI_LMUL1 [
(VNx16QI "TARGET_MIN_VLEN >= 128") (VNx8QI "TARGET_MIN_VLEN == 64") (VNx4QI
"TARGET_MIN_VLEN == 32")
])
(define_insn "@pred_reduc_<reduc><VQI:mode><VQI_LMUL1:mode>"
[(set (match_operand:VQI_LMUL1 0 "register_operand" "=vr, vr")
(unspec:VQI_LMUL1
[(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
(match_operand 5 "vector_length_operand" " rK, rK")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(any_reduc:VQI
(vec_duplicate:VQI
(vec_select:<VEL>
(match_operand:VQI_LMUL1 4 "register_operand" " vr, vr")
(parallel [(const_int 0)])))
(match_operand:VQI 3 "register_operand" " vr, vr"))
(match_operand:VQI_LMUL1 2 "vector_merge_operand" " vu, 0")]
UNSPEC_REDUC))]
"TARGET_VECTOR"
"vred<reduc>.vs\t%0,%3,%4%p1"
[(set_attr "type" "vired")
(set_attr "mode" "<VQI:MODE>")])
next prev parent reply other threads:[~2023-06-15 7:59 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-15 7:44 [Bug c/110265] New: RISC-V: ICE when build RVV intrinsic with "-march=rv32gc_zve64d -mabi=ilp32d" pan2.li at intel dot com
2023-06-15 7:59 ` juzhe.zhong at rivai dot ai [this message]
2023-06-16 23:37 ` [Bug c/110265] RISC-V: ICE when build RVV intrinsic integer reduction with "-march=rv32gc_zve64d -mabi=ilp32d", both GCC 14 and 13 cvs-commit at gcc dot gnu.org
2024-01-18 3:01 ` [Bug target/110265] " pan2.li at intel dot com
2024-01-20 17:24 ` pinskia at gcc dot gnu.org
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