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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org> To: gcc-bugs@gcc.gnu.org Subject: [Bug rtl-optimization/110717] Double-word sign-extension missed-optimization Date: Wed, 13 Dec 2023 13:37:44 +0000 [thread overview] Message-ID: <bug-110717-4-R1hM1Qeljf@http.gcc.gnu.org/bugzilla/> (raw) In-Reply-To: <bug-110717-4@http.gcc.gnu.org/bugzilla/> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110717 --- Comment #17 from GCC Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Roger Sayle <sayle@gcc.gnu.org>: https://gcc.gnu.org/g:ff8d0ce17fb585a29a83349acbc67b2dd3556629 commit r14-6495-gff8d0ce17fb585a29a83349acbc67b2dd3556629 Author: Roger Sayle <roger@nextmovesoftware.com> Date: Wed Dec 13 13:36:44 2023 +0000 ARC: Add *extvsi_n_0 define_insn_and_split for PR 110717. This patch improves the code generated for bitfield sign extensions on ARC cpus without a barrel shifter. Compiling the following test case: int foo(int x) { return (x<<27)>>27; } with -O2 -mcpu=em, generates two loops: foo: mov lp_count,27 lp 2f add r0,r0,r0 nop 2: # end single insn loop mov lp_count,27 lp 2f asr r0,r0 nop 2: # end single insn loop j_s [blink] and the closely related test case: struct S { int a : 5; }; int bar (struct S *p) { return p->a; } generates the slightly better: bar: ldb_s r0,[r0] mov_s r2,0 ;3 add3 r0,r2,r0 sexb_s r0,r0 asr_s r0,r0 asr_s r0,r0 j_s.d [blink] asr_s r0,r0 which uses 6 instructions to perform this particular sign extension. It turns out that sign extensions can always be implemented using at most three instructions on ARC (without a barrel shifter) using the idiom ((x&mask)^msb)-msb [as described in section "2-5 Sign Extension" of Henry Warren's book "Hacker's Delight"]. Using this, the sign extensions above on ARC's EM both become: bmsk_s r0,r0,4 xor r0,r0,16 sub r0,r0,16 which takes about 3 cycles, compared to the ~112 cycles for the loops in foo. 2023-12-13 Roger Sayle <roger@nextmovesoftware.com> Jeff Law <jlaw@ventanamicro.com> gcc/ChangeLog * config/arc/arc.md (*extvsi_n_0): New define_insn_and_split to implement SImode sign extract using a AND, XOR and MINUS sequence. gcc/testsuite/ChangeLog * gcc.target/arc/extvsi-1.c: New test case. * gcc.target/arc/extvsi-2.c: Likewise.
next prev parent reply other threads:[~2023-12-13 13:37 UTC|newest] Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-07-18 14:32 [Bug rtl-optimization/110717] New: " jakub at gcc dot gnu.org 2023-07-18 14:33 ` [Bug rtl-optimization/110717] " jakub at gcc dot gnu.org 2023-07-18 14:54 ` jakub at gcc dot gnu.org 2023-07-19 6:38 ` rguenth at gcc dot gnu.org 2023-07-19 8:55 ` ubizjak at gmail dot com 2023-07-19 9:00 ` jakub at gcc dot gnu.org 2023-07-19 9:30 ` ubizjak at gmail dot com 2023-07-20 18:56 ` cvs-commit at gcc dot gnu.org 2023-07-20 19:03 ` ubizjak at gmail dot com 2023-07-20 19:19 ` jakub at gcc dot gnu.org 2023-07-20 19:21 ` jakub at gcc dot gnu.org 2023-07-21 9:06 ` jakub at gcc dot gnu.org 2023-07-21 10:53 ` segher at gcc dot gnu.org 2023-07-21 16:28 ` segher at gcc dot gnu.org 2023-07-21 16:46 ` pinskia at gcc dot gnu.org 2023-08-04 15:26 ` cvs-commit at gcc dot gnu.org 2023-10-30 16:18 ` cvs-commit at gcc dot gnu.org 2023-12-13 13:37 ` cvs-commit at gcc dot gnu.org [this message] 2024-05-07 7:41 ` rguenth at gcc dot gnu.org
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