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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org> To: gcc-bugs@gcc.gnu.org Subject: [Bug rtl-optimization/110717] Double-word sign-extension missed-optimization Date: Thu, 20 Jul 2023 18:56:34 +0000 [thread overview] Message-ID: <bug-110717-4-QAJwSZlxZd@http.gcc.gnu.org/bugzilla/> (raw) In-Reply-To: <bug-110717-4@http.gcc.gnu.org/bugzilla/> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110717 --- Comment #7 from CVS Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Uros Bizjak <uros@gcc.gnu.org>: https://gcc.gnu.org/g:b50a851eef4b70aabf28fa875d9b2a302d17b66a commit r14-2684-gb50a851eef4b70aabf28fa875d9b2a302d17b66a Author: Uros Bizjak <ubizjak@gmail.com> Date: Thu Jul 20 20:54:51 2023 +0200 i386: Double-word sign-extension missed-optimization [PR110717] When sign-extending the value in a double-word register pair using shift and ashiftrt sequence with the same count immediate value less than word width, there is no need to shift the lower word of the value. The sign-extension could be limited to the upper word, but we uselessly shift the lower word with it as well: movq %rdi, %rax movq %rsi, %rdx shldq $59, %rdi, %rdx salq $59, %rax shrdq $59, %rdx, %rax sarq $59, %rdx ret for -m64 and movl 4(%esp), %eax movl 8(%esp), %edx shldl $27, %eax, %edx sall $27, %eax shrdl $27, %edx, %eax sarl $27, %edx ret for -m32. The patch introduces a new post-reload splitter to provide the combined ASHIFTRT/SHIFT instruction pattern. The instruction is split to a sequence of SAL and SAR insns with the same count immediate operand: movq %rsi, %rdx movq %rdi, %rax salq $59, %rdx sarq $59, %rdx ret Some complication is required to properly handle STV transform, where we emit a sequence with DImode PSLLQ and PSRAQ insns for 32-bit AVX512VL targets when profitable. The patch also fixes a small oversight and enables STV transform of SImode ASHIFTRT to PSRAD also for SSE2 targets. PR target/110717 gcc/ChangeLog: * config/i386/i386-features.cc (general_scalar_chain::compute_convert_gain): Calculate gain for extend higpart case. (general_scalar_chain::convert_op): Handle ASHIFTRT/ASHIFT combined RTX. (general_scalar_to_vector_candidate_p): Enable ASHIFTRT for SImode for SSE2 targets. Handle ASHIFTRT/ASHIFT combined RTX. * config/i386/i386.md (*extend<dwi>2_doubleword_highpart): New define_insn_and_split pattern. (*extendv2di2_highpart_stv): Ditto. gcc/testsuite/ChangeLog: * gcc.target/i386/pr110717.c: New test.
next prev parent reply other threads:[~2023-07-20 18:56 UTC|newest] Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-07-18 14:32 [Bug rtl-optimization/110717] New: " jakub at gcc dot gnu.org 2023-07-18 14:33 ` [Bug rtl-optimization/110717] " jakub at gcc dot gnu.org 2023-07-18 14:54 ` jakub at gcc dot gnu.org 2023-07-19 6:38 ` rguenth at gcc dot gnu.org 2023-07-19 8:55 ` ubizjak at gmail dot com 2023-07-19 9:00 ` jakub at gcc dot gnu.org 2023-07-19 9:30 ` ubizjak at gmail dot com 2023-07-20 18:56 ` cvs-commit at gcc dot gnu.org [this message] 2023-07-20 19:03 ` ubizjak at gmail dot com 2023-07-20 19:19 ` jakub at gcc dot gnu.org 2023-07-20 19:21 ` jakub at gcc dot gnu.org 2023-07-21 9:06 ` jakub at gcc dot gnu.org 2023-07-21 10:53 ` segher at gcc dot gnu.org 2023-07-21 16:28 ` segher at gcc dot gnu.org 2023-07-21 16:46 ` pinskia at gcc dot gnu.org 2023-08-04 15:26 ` cvs-commit at gcc dot gnu.org 2023-10-30 16:18 ` cvs-commit at gcc dot gnu.org 2023-12-13 13:37 ` cvs-commit at gcc dot gnu.org 2024-05-07 7:41 ` rguenth at gcc dot gnu.org
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