[Bug rtl-optimization/110717] New: Double-word sign-extension missed-optimization

["jakub at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110717

            Bug ID: 110717
           Summary: Double-word sign-extension missed-optimization
           Product: gcc
           Version: 14.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: rtl-optimization
          Assignee: unassigned at gcc dot gnu.org
          Reporter: jakub at gcc dot gnu.org
  Target Milestone: ---

While working on _BitInt, I've noticed that we don't emit very good code at
least on x86_64 -m64/-m32 -O2 for:
#ifdef __SIZEOF_INT128__
unsigned __int128
foo (unsigned __int128 x)
{
  x <<= 59;
  return ((__int128) x) >> 59;
}
#else
unsigned long long
foo (unsigned long long x)
{
  x <<= 27;
  return ((long long) x) >> 27;
}
#endif

The sign-extension from 69 resp. 37 bits could be limited solely to the upper
word,
but we uselessly shift the lower word with it as well:
        movq    %rdi, %rax
        movq    %rsi, %rdx
        shldq   $59, %rdi, %rdx
        salq    $59, %rax
        shrdq   $59, %rdx, %rax
        sarq    $59, %rdx
        ret
for -m64 and
        movl    4(%esp), %eax
        movl    8(%esp), %edx
        shldl   $27, %eax, %edx
        sall    $27, %eax
        shrdl   $27, %edx, %eax
        sarl    $27, %edx
        ret
for -m32.
LLVM emits even more horrible code for -m64, but
        movl    4(%esp), %eax
        movl    8(%esp), %edx
        shll    $27, %edx
        sarl    $27, %edx
        retl
for -m32, which looks to me like what we want.