[Bug target/110741] New: vec_ternarylogic intrinsic generates incorrect code on POWER10 target when compiled with GCC

[Bug target/110741] New: vec_ternarylogic intrinsic generates incorrect code on POWER10 target when compiled with GCC

[john_platts at hotmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110741

            Bug ID: 110741
           Summary: vec_ternarylogic intrinsic generates incorrect code on
                    POWER10 target when compiled with GCC
           Product: gcc
           Version: 12.1.1
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: john_platts at hotmail dot com
  Target Milestone: ---

Created attachment 55582
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=55582&action=edit
POWER10 ternary logic test program

The vec_ternarylogic intrinsic generates incorrect code when compiled with GCC.

The bug does not occur when vec_ternarylogic is compiled with Clang.

The attached ppc10_ternary_logic_tester_071923.cpp program needs to be compiled
with the -mcpu=power10 compiler option.

Here is the expected output when running the compiled version of the attached
ppc10_ternary_logic_tester_071923.cpp program:
$./ppc10_ternary_logic_tester_071923 0xD8 0x6C 0x56 0xB6
VSXTernaryLogic(0xd8, 0x6c, 0x56, 182) = 0xffffffffffffff3d

Here is the actual output when running the attached
ppc10_ternary_logic_tester_071923.cpp program that is compiled with a version
of GCC that has the compiler bug (if it is not compiled with the
-DUSE_INLINE_ASM_VSX_TERNLOG option):
$./ppc10_ternary_logic_tester_071923 0xD8 0x6C 0x56 0xB6
VSXTernaryLogic(0xd8, 0x6c, 0x56, 182) = 0xffffffffffffffff

If the ppc10_ternary_logic_tester_071923.cpp program is compiled with the
-DUSE_INLINE_ASM_VSX_TERNLOG option with GCC, then the expected output is
generated as inline assembly is used instead of the vec_ternarylogic intrinsic.

Another snippet that shows the incorrect code being generated for the
vec_ternarylogic intrinsic on POWER10 with GCC can be found at
https://godbolt.org/z/3666bacxs

[Bug target/110741] vec_ternarylogic intrinsic generates incorrect code on POWER10 target when compiled with GCC

[linkw at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110741

Kewen Lin <linkw at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |ASSIGNED
           Assignee|unassigned at gcc dot gnu.org      |linkw at gcc dot gnu.org
                 CC|                            |linkw at gcc dot gnu.org
     Ever confirmed|0                           |1
   Last reconfirmed|                            |2023-07-21

--- Comment #1 from Kewen Lin <linkw at gcc dot gnu.org> ---
Confirmed.

[Bug target/110741] vec_ternarylogic intrinsic generates incorrect code on POWER10 target when compiled with GCC

[linkw at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110741

Kewen Lin <linkw at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |bergner at gcc dot gnu.org,
                   |                            |segher at gcc dot gnu.org

--- Comment #2 from Kewen Lin <linkw at gcc dot gnu.org> ---
It exposed one issue on xxeval output vsx operands' format, can be fixed with:

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 0c269e4e8d9..1a87f1c0b63 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -6586,7 +6586,7 @@ (define_insn "xxeval"
                       (match_operand:QI 4 "u8bit_cint_operand" "n")]
                      UNSPEC_XXEVAL))]
    "TARGET_POWER10"
-   "xxeval %0,%1,%2,%3,%4"
+   "xxeval %x0,%x1,%x2,%x3,%4"
    [(set_attr "type" "vecperm")
     (set_attr "prefixed" "yes")])

[Bug target/110741] vec_ternarylogic intrinsic generates incorrect code on POWER10 target when compiled with GCC

[bergner at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110741

--- Comment #3 from Peter Bergner <bergner at gcc dot gnu.org> ---
(In reply to Kewen Lin from comment #2)
> It exposed one issue on xxeval output vsx operands' format, can be fixed
> with:
> 
> diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
> index 0c269e4e8d9..1a87f1c0b63 100644
> --- a/gcc/config/rs6000/vsx.md
> +++ b/gcc/config/rs6000/vsx.md
> @@ -6586,7 +6586,7 @@ (define_insn "xxeval"
>                        (match_operand:QI 4 "u8bit_cint_operand" "n")]
>                       UNSPEC_XXEVAL))]
>     "TARGET_POWER10"
> -   "xxeval %0,%1,%2,%3,%4"
> +   "xxeval %x0,%x1,%x2,%x3,%4"
>     [(set_attr "type" "vecperm")
>      (set_attr "prefixed" "yes")])

Good catch. I consider that an "obvious" fix.  Please check for needed
backports.

[Bug target/110741] vec_ternarylogic intrinsic generates incorrect code on POWER10 target when compiled with GCC

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110741

--- Comment #4 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Kewen Lin <linkw@gcc.gnu.org>:

https://gcc.gnu.org/g:96a839233ced3a0bfc3d5492a6d8b102e6981472

commit r14-2781-g96a839233ced3a0bfc3d5492a6d8b102e6981472
Author: Kewen Lin <linkw@linux.ibm.com>
Date:   Wed Jul 26 03:42:29 2023 -0500

    rs6000: Correct vsx operands output for xxeval [PR110741]

    PR110741 exposes one issue that we didn't use the correct
    character for vsx operands in output operand substitution,
    consequently it can map to the wrong registers which hold
    some unexpected values.

            PR target/110741

    gcc/ChangeLog:

            * config/rs6000/vsx.md (define_insn xxeval): Correct vsx
            operands output with "x".

    gcc/testsuite/ChangeLog:

            * g++.target/powerpc/pr110741.C: New test.

[Bug target/110741] vec_ternarylogic intrinsic generates incorrect code on POWER10 target when compiled with GCC

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110741

--- Comment #5 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-11 branch has been updated by Kewen Lin <linkw@gcc.gnu.org>:

https://gcc.gnu.org/g:2ad68e7ce034f74ac0e74b6140b3207c21b6573a

commit r11-10931-g2ad68e7ce034f74ac0e74b6140b3207c21b6573a
Author: Kewen Lin <linkw@linux.ibm.com>
Date:   Wed Jul 26 03:42:29 2023 -0500

    rs6000: Correct vsx operands output for xxeval [PR110741]

    PR110741 exposes one issue that we didn't use the correct
    character for vsx operands in output operand substitution,
    consequently it can map to the wrong registers which hold
    some unexpected values.

            PR target/110741

    gcc/ChangeLog:

            * config/rs6000/altivec.md (define_insn xxeval): Correct vsx
            operands output with "x".

    gcc/testsuite/ChangeLog:

            * g++.target/powerpc/pr110741.C: New test.

    (cherry picked from commit 96a839233ced3a0bfc3d5492a6d8b102e6981472)

[Bug target/110741] vec_ternarylogic intrinsic generates incorrect code on POWER10 target when compiled with GCC

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110741

--- Comment #6 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-12 branch has been updated by Kewen Lin <linkw@gcc.gnu.org>:

https://gcc.gnu.org/g:e58899645f09fb26fbca03ed8b9b13f162ff32dc

commit r12-9795-ge58899645f09fb26fbca03ed8b9b13f162ff32dc
Author: Kewen Lin <linkw@linux.ibm.com>
Date:   Wed Jul 26 03:42:29 2023 -0500

    rs6000: Correct vsx operands output for xxeval [PR110741]

    PR110741 exposes one issue that we didn't use the correct
    character for vsx operands in output operand substitution,
    consequently it can map to the wrong registers which hold
    some unexpected values.

            PR target/110741

    gcc/ChangeLog:

            * config/rs6000/vsx.md (define_insn xxeval): Correct vsx
            operands output with "x".

    gcc/testsuite/ChangeLog:

            * g++.target/powerpc/pr110741.C: New test.

    (cherry picked from commit 96a839233ced3a0bfc3d5492a6d8b102e6981472)

[Bug target/110741] vec_ternarylogic intrinsic generates incorrect code on POWER10 target when compiled with GCC

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110741

--- Comment #7 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-13 branch has been updated by Kewen Lin <linkw@gcc.gnu.org>:

https://gcc.gnu.org/g:cf10790c24b302b3265afdfc96abdfc35932fbd0

commit r13-7677-gcf10790c24b302b3265afdfc96abdfc35932fbd0
Author: Kewen Lin <linkw@linux.ibm.com>
Date:   Wed Jul 26 03:42:29 2023 -0500

    rs6000: Correct vsx operands output for xxeval [PR110741]

    PR110741 exposes one issue that we didn't use the correct
    character for vsx operands in output operand substitution,
    consequently it can map to the wrong registers which hold
    some unexpected values.

            PR target/110741

    gcc/ChangeLog:

            * config/rs6000/vsx.md (define_insn xxeval): Correct vsx
            operands output with "x".

    gcc/testsuite/ChangeLog:

            * g++.target/powerpc/pr110741.C: New test.

    (cherry picked from commit 96a839233ced3a0bfc3d5492a6d8b102e6981472)

[Bug target/110741] vec_ternarylogic intrinsic generates incorrect code on POWER10 target when compiled with GCC

[linkw at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110741

Kewen Lin <linkw at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|ASSIGNED                    |RESOLVED
         Resolution|---                         |FIXED

--- Comment #8 from Kewen Lin <linkw at gcc dot gnu.org> ---
Should be fixed everywhere.