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From: "sainan+gcc.bugzilla at calamity dot gg" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug middle-end/110773] [Aarch64] crash (SIGBUS) due to atomic instructions on under-aligned memory
Date: Thu, 04 Apr 2024 17:09:09 +0000	[thread overview]
Message-ID: <bug-110773-4-3wARJMwRbV@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-110773-4@http.gcc.gnu.org/bugzilla/>

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110773

--- Comment #5 from Sainan <sainan+gcc.bugzilla at calamity dot gg> ---
(In reply to Wilco from comment #4)
> The atomic will also set correct struct alignment.

My thinking was that maybe this is not the case (= standard library issue)
since both GCC and Clang seem to be causing this issue, but manually adding
alignas(16) also didn't help.

> You would get a crash if you build for LSE so you get a LDADDAL instruction
> and then run it on a CPU that doesn't. So try -mcpu=native and it should
> work.

-mcpu=native didn't fix the SIGBUS, only removed __aarch64_ldadd4_acq_rel from
the stack trace.

FWIW, the CPU on this system where I get the SIGBUS is Cortex-A76, which should
support LSE and atomics, but it seems everytime it encounters atomics, it just
throws a SIGBUS. It works fine on Snapdragon 8cx Gen 3.

  parent reply	other threads:[~2024-04-04 17:09 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-07-21 23:46 [Bug target/110773] New: " scw-gcc at google dot com
2023-07-22  0:02 ` [Bug middle-end/110773] " pinskia at gcc dot gnu.org
2023-09-07 14:38 ` wilco at gcc dot gnu.org
2024-04-04 10:44 ` sainan+gcc.bugzilla at calamity dot gg
2024-04-04 10:59 ` wilco at gcc dot gnu.org
2024-04-04 17:09 ` sainan+gcc.bugzilla at calamity dot gg [this message]
2024-04-04 17:25 ` wilco at gcc dot gnu.org
2024-04-04 17:45 ` sainan+gcc.bugzilla at calamity dot gg
2024-04-04 17:54 ` wilco at gcc dot gnu.org
2024-04-04 18:01 ` sainan+gcc.bugzilla at calamity dot gg

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