[Bug c/111232] New: RISC-V: Failed to combine vwmul + vadd into vwmacc

[Bug c/111232] New: RISC-V: Failed to combine vwmul + vadd into vwmacc

[juzhe.zhong at rivai dot ai]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111232

            Bug ID: 111232
           Summary: RISC-V: Failed to combine vwmul + vadd into vwmacc
           Product: gcc
           Version: 14.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: c
          Assignee: unassigned at gcc dot gnu.org
          Reporter: juzhe.zhong at rivai dot ai
  Target Milestone: ---

#include <stdlib.h>
#define N 64

#define DOT -21856

signed char X[N] __attribute__ ((__aligned__(__BIGGEST_ALIGNMENT__))) =
{0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63};
signed char Y[N] __attribute__ ((__aligned__(__BIGGEST_ALIGNMENT__))) =
{64,63,62,61,60,59,58,57,56,55,54,53,52,51,50,49,48,47,46,45,44,43,42,41,40,39,38,37,36,35,34,33,32,31,30,29,28,27,26,25,24,23,22,21,20,19,18,17,16,15,14,13,12,11,10,9,8,7,6,5,4,3,2,1};

/* char->short->short dot product.
   The dot-product pattern should be detected.
   Should be vectorized on vect_sdot_qi targets (targets that support 
   dot-product of signed char).  
   This test currently fails to vectorize on targets that support
   dot-product of chars into and int accumulator.
   Can also be vectorized as widening-mult + summation,
   or with type-conversion support.
 */
__attribute__ ((noinline)) short
foo(int len) {
  int i;
  short result = 0;

  for (i=0; i<len; i++) {
    result += (X[i] * Y[i]);
  }
  return result;
}

ASM:

        vsetvli a5,a0,e8,mf2,ta,ma
        vle8.v  v4,0(a4)
        vle8.v  v3,0(a3)
        sub     a0,a0,a5
        vsetvli a2,zero,e8,mf2,ta,ma
        add     a4,a4,a5
        vwmul.vv        v2,v4,v3
        add     a3,a3,a5
        vsetvli zero,a5,e16,m1,tu,ma
        vadd.vv v1,v2,v1
        bne     a0,zero,.L8
        vsetvli a2,zero,e16,m1,ta,ma
        vmv.s.x v2,zero
        vredsum.vs      v1,v1,v2
        vmv.x.s a0,v1
        ret

It should be vwmacc instead of vwmul + vadd.

[Bug target/111232] RISC-V: Failed to combine vwmul + vadd into vwmacc

[lehua.ding at rivai dot ai]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111232

--- Comment #1 from Lehua Ding <lehua.ding at rivai dot ai> ---
reproduce on compiler explorer: https://godbolt.org/z/Mq3bzajn6

[Bug target/111232] RISC-V: Failed to combine vwmul + vadd into vwmacc

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111232

--- Comment #2 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The trunk branch has been updated by Lehua Ding <lhtin@gcc.gnu.org>:

https://gcc.gnu.org/g:9ee40b9a7bee83394fc7ba6fef71cb76d91b49c8

commit r14-3735-g9ee40b9a7bee83394fc7ba6fef71cb76d91b49c8
Author: Lehua Ding <lehua.ding@rivai.ai>
Date:   Mon Sep 4 17:15:08 2023 +0800

    RISC-V: Keep vlmax vector operators in simple form until split1 pass

    This patch keep vlmax vector pattern in simple before split1 pass which
    will allow more optimization (e.g. combine) before split1 pass.
    This patch changes the vlmax pattern in autovec.md to define_insn_and_split
    as much as possible and clean up some combine patterns that are no longer
needed.
    This patch also fixed PR111232 bug which was caused by a combined failed.

            PR target/111232

    gcc/ChangeLog:

            * config/riscv/autovec-opt.md
(@pred_single_widen_mul<any_extend:su><mode>):
            Delete.
            (*pred_widen_mulsu<mode>): Delete.
            (*pred_single_widen_mul<mode>): Delete.
            (*dual_widen_<any_widen_binop:optab><any_extend:su><mode>):
            Add new combine patterns.
            (*single_widen_sub<any_extend:su><mode>): Ditto.
            (*single_widen_add<any_extend:su><mode>): Ditto.
            (*single_widen_mult<any_extend:su><mode>): Ditto.
            (*dual_widen_mulsu<mode>): Ditto.
            (*dual_widen_mulus<mode>): Ditto.
            (*dual_widen_<optab><mode>): Ditto.
            (*single_widen_add<mode>): Ditto.
            (*single_widen_sub<mode>): Ditto.
            (*single_widen_mult<mode>): Ditto.
            * config/riscv/autovec.md (<optab><mode>3):
            Change define_expand to define_insn_and_split.
            (<optab><mode>2): Ditto.
            (abs<mode>2): Ditto.
            (smul<mode>3_highpart): Ditto.
            (umul<mode>3_highpart): Ditto.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/autovec/widen/widen-4.c: Add more testcases.
            * gcc.target/riscv/rvv/autovec/widen/widen-complicate-4.c: Ditto.
            * gcc.target/riscv/rvv/autovec/pr111232.c: New test.

[Bug target/111232] RISC-V: Failed to combine vwmul + vadd into vwmacc

[juzhe.zhong at rivai dot ai]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111232

JuzheZhong <juzhe.zhong at rivai dot ai> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |RESOLVED
         Resolution|---                         |FIXED

--- Comment #3 from JuzheZhong <juzhe.zhong at rivai dot ai> ---
Fixed.