[Bug target/111720] RISC-V: Ugly codegen in RVV

["juzhe.zhong at rivai dot ai" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111720

--- Comment #13 from JuzheZhong <juzhe.zhong at rivai dot ai> ---
Confirm ARM SVE has the same issue:

https://godbolt.org/z/TjcaM6xsP

#include<arm_sve.h>
void fn(uint8_t * __restrict out) {

    uint8_t arr[32] = {1, 2, 7, 1, 3, 4, 5, 3, 1, 0, 1, 2, 4, 4, 9, 9, 1, 2, 7,
1, 3, 4, 5, 3, 1, 0, 1, 2, 4, 4, 9, 9};
    uint8_t m = 1;

    svint8_t varr = *(svint8_t*)arr;
    *(svint8_t*)out = varr;
}

ARM GCC:

fn:
        adrp    x1, .LANCHOR0
        add     x1, x1, :lo12:.LANCHOR0
        sub     sp, sp, #32
        ptrue   p7.b, all
        ldp     q31, q30, [x1]   -----> redundant stack spillings.
        stp     q31, q30, [sp]   -----> redundant stack spillings.
        ld1b    z31.b, p7/z, [sp]
        st1b    z31.b, p7, [x0]
        add     sp, sp, 32
        ret

ARM clang:

fn:                                     // @fn
        ptrue   p0.b
        adrp    x8, .L__const.fn.arr
        add     x8, x8, :lo12:.L__const.fn.arr
        ld1b    { z0.b }, p0/z, [x8]
        st1b    { z0.b }, p0, [x0]
        ret

Hi, Richard. Could you comment this issue ?
Thanks.