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From: "juzhe.zhong at rivai dot ai" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/111720] RISC-V: Ugly codegen in RVV
Date: Sat, 07 Oct 2023 22:47:22 +0000 [thread overview]
Message-ID: <bug-111720-4-nyjUL1lumv@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-111720-4@http.gcc.gnu.org/bugzilla/>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111720
--- Comment #8 from JuzheZhong <juzhe.zhong at rivai dot ai> ---
(In reply to Andrew Pinski from comment #6)
> I suspect if __riscv_vle8_v_u8m1 gets lowered into a load on the gimple
> level, it might just work ...
>
> But it gets expanded as:
> (insn 14 13 0 (set (reg/v:RVVM1QI 134 [ varrD.56526 ])
> (if_then_else:RVVM1QI (unspec:RVVMF8BI [
> (const_vector:RVVMF8BI repeat [
> (const_int 1 [0x1])
> ])
> (reg:DI 145)
> (const_int 2 [0x2]) repeated x2
> (const_int 0 [0])
> (reg:SI 66 vl)
> (reg:SI 67 vtype)
> ] UNSPEC_VPREDICATE)
> (mem:RVVM1QI (reg:DI 144) [0 S[16, 16] A8])
> (unspec:RVVM1QI [
> (reg:SI 0 zero)
> ] UNSPEC_VUNDEF))) "/app/example.c":7:23 -1
> (nil))
>
> That seems complex.
You mean the normal load MEM_REF in GCC ?
I don't think we can do that since this intrinsic is defined with mask, len,
else value,...etc.
next prev parent reply other threads:[~2023-10-07 22:47 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-07 22:28 [Bug c/111720] New: " juzhe.zhong at rivai dot ai
2023-10-07 22:34 ` [Bug target/111720] " juzhe.zhong at rivai dot ai
2023-10-07 22:36 ` pinskia at gcc dot gnu.org
2023-10-07 22:38 ` juzhe.zhong at rivai dot ai
2023-10-07 22:41 ` juzhe.zhong at rivai dot ai
2023-10-07 22:43 ` juzhe.zhong at rivai dot ai
2023-10-07 22:44 ` pinskia at gcc dot gnu.org
2023-10-07 22:44 ` pinskia at gcc dot gnu.org
2023-10-07 22:47 ` juzhe.zhong at rivai dot ai [this message]
2023-10-07 22:49 ` juzhe.zhong at rivai dot ai
2023-10-07 22:51 ` pinskia at gcc dot gnu.org
2023-10-07 22:55 ` juzhe.zhong at rivai dot ai
2023-10-07 23:09 ` juzhe.zhong at rivai dot ai
2023-10-17 8:26 ` juzhe.zhong at rivai dot ai
2023-10-18 3:29 ` pan2.li at intel dot com
2023-10-19 2:07 ` juzhe.zhong at rivai dot ai
2023-10-19 6:37 ` rguenth at gcc dot gnu.org
2023-10-19 7:45 ` juzhe.zhong at rivai dot ai
2023-10-19 11:16 ` rguenth at gcc dot gnu.org
2023-10-19 11:30 ` juzhe.zhong at rivai dot ai
2023-10-19 11:34 ` rguenther at suse dot de
2023-10-19 11:58 ` juzhe.zhong at rivai dot ai
2023-10-19 12:02 ` rguenther at suse dot de
2023-10-19 12:08 ` juzhe.zhong at rivai dot ai
2023-10-19 12:20 ` rguenther at suse dot de
2023-10-19 12:38 ` juzhe.zhong at rivai dot ai
2023-10-19 13:30 ` rguenther at suse dot de
2023-11-01 7:33 ` pan2.li at intel dot com
2023-11-06 10:27 ` rguenth at gcc dot gnu.org
2023-11-06 10:44 ` juzhe.zhong at rivai dot ai
2023-11-23 1:20 ` cvs-commit at gcc dot gnu.org
2023-11-23 1:29 ` pan2.li at intel dot com
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