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* [Bug c/111721] New: RISC-V: Failed to SLP for gather_load in RVV
@ 2023-10-07 23:18 juzhe.zhong at rivai dot ai
2023-11-03 11:27 ` [Bug target/111721] " cvs-commit at gcc dot gnu.org
2023-11-03 12:13 ` juzhe.zhong at rivai dot ai
0 siblings, 2 replies; 3+ messages in thread
From: juzhe.zhong at rivai dot ai @ 2023-10-07 23:18 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111721
Bug ID: 111721
Summary: RISC-V: Failed to SLP for gather_load in RVV
Product: gcc
Version: 14.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: c
Assignee: unassigned at gcc dot gnu.org
Reporter: juzhe.zhong at rivai dot ai
Target Milestone: ---
https://godbolt.org/z/d5TPa5e5s
void __attribute__((noipa))
f (int *restrict y, int *restrict x, int *restrict indices, int n)
{
for (int i = 0; i < n; ++i)
{
y[i * 2] = x[indices[i * 2]] + 1;
y[i * 2 + 1] = x[indices[i * 2 + 1]] + 2;
}
}
RVV ASM:
f:
ble a3,zero,.L5
.L3:
vsetvli a5,a3,e32,m1,ta,ma
vlseg2e32.v v2,(a2) ----> VEC_LOAD_LANES
vsetivli zero,4,e32,m1,ta,ma
vsll.vi v4,v2,2
vsll.vi v1,v3,2
vsetvli zero,a5,e32,m1,ta,ma
vluxei32.v v4,(a1),v4
vluxei32.v v1,(a1),v1
vsetivli zero,4,e32,m1,ta,ma
slli a4,a5,3
vadd.vi v2,v4,1
vadd.vi v3,v1,2
sub a3,a3,a5
vsetvli zero,a5,e32,m1,ta,ma
vsseg2e32.v v2,(a0) ----> VEC_STORE_LANES
add a2,a2,a4
add a0,a0,a4
bne a3,zero,.L3
.L5:
ret
Comparing to aarch64 which can SLP, RVV geneates expensive
load_lanes/store_lanes.
This is because RVV is using MASK_LEN_GATHER_LOAD that we currently can didn't
support SLP for it.
^ permalink raw reply [flat|nested] 3+ messages in thread
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2023-10-07 23:18 [Bug c/111721] New: RISC-V: Failed to SLP for gather_load in RVV juzhe.zhong at rivai dot ai
2023-11-03 11:27 ` [Bug target/111721] " cvs-commit at gcc dot gnu.org
2023-11-03 12:13 ` juzhe.zhong at rivai dot ai
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