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From: "juzhe.zhong at rivai dot ai" <gcc-bugzilla@gcc.gnu.org> To: gcc-bugs@gcc.gnu.org Subject: [Bug tree-optimization/111970] [14 regression] SLP for non-IFN gathers result in RISC-V test failure on gather since r14-4745-gbeab5b95c58145 Date: Mon, 20 Nov 2023 08:10:49 +0000 [thread overview] Message-ID: <bug-111970-4-JLmxmXFtky@http.gcc.gnu.org/bugzilla/> (raw) In-Reply-To: <bug-111970-4@http.gcc.gnu.org/bugzilla/> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111970 --- Comment #14 from JuzheZhong <juzhe.zhong at rivai dot ai> --- Just confirm on aarch64 QEMU, it seems that ARM SVE has the same issue as RVV. This is the test: #include <stdint-gcc.h> #define TEST_LOOP(DATA_TYPE, INDEX_TYPE) \ void __attribute__ ((noinline, noclone)) \ f_##DATA_TYPE##_##INDEX_TYPE (DATA_TYPE *restrict y, DATA_TYPE *restrict x, \ INDEX_TYPE *restrict index) \ { \ for (int i = 0; i < 100; ++i) \ { \ y[i * 2] = x[index[i * 2]] + 1; \ y[i * 2 + 1] = x[index[i * 2 + 1]] + 2; \ } \ } TEST_LOOP (int16_t, int8_t) #include <assert.h> int main (void) { #define RUN_LOOP(DATA_TYPE, INDEX_TYPE) \ DATA_TYPE dest_##DATA_TYPE##_##INDEX_TYPE[202] = {0}; \ DATA_TYPE src_##DATA_TYPE##_##INDEX_TYPE[202] = {0}; \ INDEX_TYPE index_##DATA_TYPE##_##INDEX_TYPE[202] = {0}; \ for (int i = 0; i < 202; i++) \ { \ src_##DATA_TYPE##_##INDEX_TYPE[i] \ = (DATA_TYPE) ((i * 19 + 735) & (sizeof (DATA_TYPE) * 7 - 1)); \ index_##DATA_TYPE##_##INDEX_TYPE[i] = (i * 7) % (55); \ } \ f_##DATA_TYPE##_##INDEX_TYPE (dest_##DATA_TYPE##_##INDEX_TYPE, \ src_##DATA_TYPE##_##INDEX_TYPE, \ index_##DATA_TYPE##_##INDEX_TYPE); \ for (int i = 0; i < 100; i++) \ { \ assert (dest_##DATA_TYPE##_##INDEX_TYPE[i * 2] \ == (src_##DATA_TYPE##_##INDEX_TYPE \ [index_##DATA_TYPE##_##INDEX_TYPE[i * 2]] \ + 1)); \ assert (dest_##DATA_TYPE##_##INDEX_TYPE[i * 2 + 1] \ == (src_##DATA_TYPE##_##INDEX_TYPE \ [index_##DATA_TYPE##_##INDEX_TYPE[i * 2 + 1]] \ + 2)); \ } RUN_LOOP (int16_t, int8_t) return 0; } compile: -march=armv8-a+sve -O3 -msve-vector-bits=256 -specs=rdimon.specs QEMU:sve-default-vector-length=256 The configuration above passed. However, I tried -march=armv8-a+sve -O3 -msve-vector-bits=512 -fno-vect-cost-model -specs=rdimon.specs QEMU:sve-default-vector-length=512 This configuration failed like RVV: assertion "dest_int16_t_int8_t[i * 2] == (src_int16_t_int8_t [index_int16_t_int8_t[i * 2]] + 1)" failed: file "tmp.c", line 52, function: main The reason I experiment on ARM SVE with vector-length = 512bits, because I checked the dump IR on ARM SVE which is similiar with RVV: https://godbolt.org/z/x74z7obYT Hi, @Tamar. Could you double-check whether my analysis (This bug not only happens on RVV, but also on ARM SVE) is correct or not ?
next prev parent reply other threads:[~2023-11-20 8:10 UTC|newest] Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-10-25 2:02 [Bug c/111970] New: [tree-optimization] SLP for non-IFN gathers result in RISC-V test failure on gather pan2.li at intel dot com 2023-10-25 2:03 ` [Bug c/111970] " pan2.li at intel dot com 2023-10-25 2:53 ` [Bug tree-optimization/111970] [14 regression] SLP for non-IFN gathers result in RISC-V test failure on gather since r14-4745-gbeab5b95c58145 pan2.li at intel dot com 2023-10-25 8:05 ` pan2.li at intel dot com 2023-10-27 12:29 ` rguenth at gcc dot gnu.org 2023-10-27 13:03 ` pan2.li at intel dot com 2023-10-31 12:49 ` rguenth at gcc dot gnu.org 2023-10-31 14:07 ` pan2.li at intel dot com 2023-10-31 14:16 ` pan2.li at intel dot com 2023-11-13 12:42 ` rguenth at gcc dot gnu.org 2023-11-13 22:07 ` juzhe.zhong at rivai dot ai 2023-11-20 6:49 ` juzhe.zhong at rivai dot ai 2023-11-20 6:51 ` juzhe.zhong at rivai dot ai 2023-11-20 6:52 ` juzhe.zhong at rivai dot ai 2023-11-20 8:10 ` juzhe.zhong at rivai dot ai [this message] 2023-11-20 8:22 ` rguenther at suse dot de 2023-11-20 8:30 ` rguenth at gcc dot gnu.org 2023-11-20 14:20 ` rguenth at gcc dot gnu.org 2023-11-20 14:58 ` rdapp at gcc dot gnu.org 2023-11-20 22:24 ` tnfchris at gcc dot gnu.org 2023-11-20 22:30 ` pinskia at gcc dot gnu.org 2023-11-20 23:56 ` pan2.li at intel dot com 2023-11-21 7:20 ` cvs-commit at gcc dot gnu.org 2023-11-21 7:24 ` rguenth at gcc dot gnu.org
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