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From: "pan2.li at intel dot com" <gcc-bugzilla@gcc.gnu.org> To: gcc-bugs@gcc.gnu.org Subject: [Bug c/111970] New: [tree-optimization] SLP for non-IFN gathers result in RISC-V test failure on gather Date: Wed, 25 Oct 2023 02:02:37 +0000 [thread overview] Message-ID: <bug-111970-4@http.gcc.gnu.org/bugzilla/> (raw) https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111970 Bug ID: 111970 Summary: [tree-optimization] SLP for non-IFN gathers result in RISC-V test failure on gather Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: c Assignee: unassigned at gcc dot gnu.org Reporter: pan2.li at intel dot com Target Milestone: --- Created attachment 56197 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=56197&action=edit Within this commit Hi Richard Biener, Recently we found one regression of RISC-V backend for gather autovec, aka gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-12.c. I narrow it down to a small piece of code like below: include <stdint-gcc.h> #define TEST_LOOP(DATA_TYPE, INDEX_TYPE) \ void __attribute__ ((noinline, noclone)) \ f_##DATA_TYPE##_##INDEX_TYPE (DATA_TYPE *restrict y, DATA_TYPE *restrict x, \ INDEX_TYPE *restrict index) \ { \ for (int i = 0; i < 100; ++i) \ { \ y[i * 2] = x[index[i * 2]] + 1; \ y[i * 2 + 1] = x[index[i * 2 + 1]] + 2; \ } \ } TEST_LOOP (float, uint8_t) The commit id beab5b95c581452adeb26efd59ae84a61fb3b429 (tree-optimization/111131 - SLP for non-IFN gathers) makes the tree generate the incorrect IR as the attachments. The data array and the index array should have the same step after vectorization. But we get incorrect offset for the second iteration. vector(32) float vect__11.11; _209 = BIT_FIELD_REF <MEM <vector(64) unsigned char> [(uint8_t *)_163], 8, 16>; then update offset for the second iteration. ivtmp.35_613 = ivtmp.35_594 + 64; // should be ivtmp = ivtmp + 32 ivtmp.38_76 = ivtmp.38_620 + 256; I also upload the tree.optimized code before and after this commit, you can check more details about it. Any more information required please feel free to let me know. Pan
next reply other threads:[~2023-10-25 2:02 UTC|newest] Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-10-25 2:02 pan2.li at intel dot com [this message] 2023-10-25 2:03 ` [Bug c/111970] " pan2.li at intel dot com 2023-10-25 2:53 ` [Bug tree-optimization/111970] [14 regression] SLP for non-IFN gathers result in RISC-V test failure on gather since r14-4745-gbeab5b95c58145 pan2.li at intel dot com 2023-10-25 8:05 ` pan2.li at intel dot com 2023-10-27 12:29 ` rguenth at gcc dot gnu.org 2023-10-27 13:03 ` pan2.li at intel dot com 2023-10-31 12:49 ` rguenth at gcc dot gnu.org 2023-10-31 14:07 ` pan2.li at intel dot com 2023-10-31 14:16 ` pan2.li at intel dot com 2023-11-13 12:42 ` rguenth at gcc dot gnu.org 2023-11-13 22:07 ` juzhe.zhong at rivai dot ai 2023-11-20 6:49 ` juzhe.zhong at rivai dot ai 2023-11-20 6:51 ` juzhe.zhong at rivai dot ai 2023-11-20 6:52 ` juzhe.zhong at rivai dot ai 2023-11-20 8:10 ` juzhe.zhong at rivai dot ai 2023-11-20 8:22 ` rguenther at suse dot de 2023-11-20 8:30 ` rguenth at gcc dot gnu.org 2023-11-20 14:20 ` rguenth at gcc dot gnu.org 2023-11-20 14:58 ` rdapp at gcc dot gnu.org 2023-11-20 22:24 ` tnfchris at gcc dot gnu.org 2023-11-20 22:30 ` pinskia at gcc dot gnu.org 2023-11-20 23:56 ` pan2.li at intel dot com 2023-11-21 7:20 ` cvs-commit at gcc dot gnu.org 2023-11-21 7:24 ` rguenth at gcc dot gnu.org
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