[Bug target/112431] RISC-V GCC-15 feature: Support register overlap on widen RVV instructions

["cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112431

--- Comment #13 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Pan Li <panli@gcc.gnu.org>:

https://gcc.gnu.org/g:27fde325d64447a3a0d5d550c5976e5f3fb6dc16

commit r14-6117-g27fde325d64447a3a0d5d550c5976e5f3fb6dc16
Author: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Date:   Mon Dec 4 21:32:06 2023 +0800

    RISC-V: Support highest-number regno overlap for widen ternary

    Consider this example:

    #include "riscv_vector.h"
    void
    foo6 (void *in, void *out)
    {
      vfloat64m8_t accum = __riscv_vle64_v_f64m8 (in, 4);
      vfloat64m4_t high_eew64 = __riscv_vget_v_f64m8_f64m4 (accum, 1);
      vint64m4_t high_eew64_i = __riscv_vreinterpret_v_f64m4_i64m4
(high_eew64);
      vint32m4_t high_eew32_i = __riscv_vreinterpret_v_i64m4_i32m4
(high_eew64_i);
      vfloat32m4_t high_eew32 = __riscv_vreinterpret_v_i32m4_f32m4
(high_eew32_i);
      vfloat64m8_t result = __riscv_vfwnmsac_vf_f64m8 (accum, 64, high_eew32,
4);
      __riscv_vse64_v_f64m8 (out, result, 4);
    }

    Before this patch:

    foo6:                                   # @foo6
            vsetivli        zero, 4, e32, m4, ta, ma
            vle64.v v8, (a0)
            lui     a0, 272384
            fmv.w.x fa5, a0
            vmv8r.v v16, v8
            vfwnmsac.vf     v16, fa5, v12
            vse64.v v16, (a1)
            ret

    After this patch:

    foo6:
    .LFB5:
            .cfi_startproc
            lui     a5,%hi(.LC0)
            flw     fa5,%lo(.LC0)(a5)
            vsetivli        zero,4,e32,m4,ta,ma
            vle64.v v8,0(a0)
            vfwnmsac.vf     v8,fa5,v12
            vse64.v v8,0(a1)
            ret

            PR target/112431

    gcc/ChangeLog:

            * config/riscv/vector.md: Add highest-number overlap support.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/base/pr112431-37.c: New test.
            * gcc.target/riscv/rvv/base/pr112431-38.c: New test.