[Bug target/112431] RISC-V GCC-15 feature: Support register overlap on widen RVV instructions

["cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112431

--- Comment #15 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Pan Li <panli@gcc.gnu.org>:

https://gcc.gnu.org/g:7e854b58084c131fceca9e8fa9dcc7469972e69d

commit r14-6400-g7e854b58084c131fceca9e8fa9dcc7469972e69d
Author: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Date:   Sat Dec 9 12:06:29 2023 +0800

    RISC-V: Support highest overlap for wv instructions

    According to RVV ISA, we can allow vwadd.wv v2, v2, v3 overlap.

    Before this patch:

            nop
            vsetivli        zero,4,e8,m4,tu,ma
            vle16.v v8,0(a0)
            vmv8r.v v0,v8
            vwsub.wv        v0,v8,v12
            nop
            addi    a4,a0,100
            vle16.v v8,0(a4)
            vmv8r.v v24,v8
            vwsub.wv        v24,v8,v12
            nop
            addi    a4,a0,200
            vle16.v v8,0(a4)
            vmv8r.v v16,v8
            vwsub.wv        v16,v8,v12
            nop

    After this patch:

            nop
            vsetivli        zero,4,e8,m4,tu,ma
            vle16.v v0,0(a0)
            vwsub.wv        v0,v0,v4
            nop
            addi    a4,a0,100
            vle16.v v24,0(a4)
            vwsub.wv        v24,v24,v28
            nop
            addi    a4,a0,200
            vle16.v v16,0(a4)
            vwsub.wv        v16,v16,v20

            PR target/112431

    gcc/ChangeLog:

            * config/riscv/vector.md: Support highest overlap for wv
instructions.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/base/pr112431-39.c: New test.
            * gcc.target/riscv/rvv/base/pr112431-40.c: New test.
            * gcc.target/riscv/rvv/base/pr112431-41.c: New test.