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* [Bug target/114307] New: [ARM] GCC generates instruction that assembler rejects
@ 2024-03-11 16:13 mkuvyrkov at gcc dot gnu.org
2024-03-11 17:34 ` [Bug target/114307] " rearnsha at gcc dot gnu.org
` (9 more replies)
0 siblings, 10 replies; 11+ messages in thread
From: mkuvyrkov at gcc dot gnu.org @ 2024-03-11 16:13 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114307
Bug ID: 114307
Summary: [ARM] GCC generates instruction that assembler rejects
Product: gcc
Version: 14.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: mkuvyrkov at gcc dot gnu.org
Target Milestone: ---
Recently added vectorization test "gcc.dg/vect/pr113576.c" fails to build for
arm-linux-gnueabihf with:
===
/home/tcwg-buildslave/workspace/tcwg_gnu_1/abe/builds/destdir/x86_64-pc-linux-gnu/bin/arm-linux-gnueabihf-gcc
--sysroot=/home/tcwg-buildslave/workspace/tcwg_gnu_1/abe/builds/destdir/x86_64-pc-linux-gnu/arm-linux-gnueabihf/libc
/home/tcwg-buildslave/workspace/tcwg_gnu_1/abe/snapshots/gcc.git~master/gcc/testsuite/gcc.dg/vect/pr113576.c
-fdiagnostics-plain-output -O3 -lm -o ./pr113576.exe
/tmp/ccRWeLpQ.s: Assembler messages:
/tmp/ccRWeLpQ.s:37: Error: selected FPU does not support instruction -- `vorr
d6,d6,d7'
compiler exited with status 1
output is:
/tmp/ccRWeLpQ.s: Assembler messages:
/tmp/ccRWeLpQ.s:37: Error: selected FPU does not support instruction -- `vorr
d6,d6,d7'
comp_output (pruned) is:
/tmp/ccRWeLpQ.s: Assembler messages:
/tmp/ccRWeLpQ.s:37: Error: selected FPU does not support instruction -- `vorr
d6,d6,d7'
FAIL: gcc.dg/vect/pr113576.c (test for excess errors)
===
The toolchain uses tip-of-trunk binutils for the build.
The relevant configure flags are: --with-float=hard --with-fpu=vfpv3-d16
--with-mode=thumb --with-tune=cortex-a9 --with-arch=armv7-a
Full configure options are at
https://ci.linaro.org/job/tcwg_gnu_cross_check_gcc--master-arm-build/lastSuccessfulBuild/artifact/artifacts/notify/configure-make.txt/*view*/
^ permalink raw reply [flat|nested] 11+ messages in thread
* [Bug target/114307] [ARM] GCC generates instruction that assembler rejects
2024-03-11 16:13 [Bug target/114307] New: [ARM] GCC generates instruction that assembler rejects mkuvyrkov at gcc dot gnu.org
@ 2024-03-11 17:34 ` rearnsha at gcc dot gnu.org
2024-03-11 17:35 ` rearnsha at gcc dot gnu.org
` (8 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: rearnsha at gcc dot gnu.org @ 2024-03-11 17:34 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114307
Richard Earnshaw <rearnsha at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Last reconfirmed| |2024-03-11
Status|UNCONFIRMED |NEW
Ever confirmed|0 |1
--- Comment #1 from Richard Earnshaw <rearnsha at gcc dot gnu.org> ---
From a full assembler dump:
.syntax divided
@ 71 "/home/rearnsha/gnusrc/gcc/master/gcc/testsuite/gcc.dg/vect/tree-vect.h" 1
vorr d6, d6, d7
@ 0 "" 2
.arm
.syntax unified
So this is a problem with the test; it shouldn't be enabled for this target.
^ permalink raw reply [flat|nested] 11+ messages in thread
* [Bug target/114307] [ARM] GCC generates instruction that assembler rejects
2024-03-11 16:13 [Bug target/114307] New: [ARM] GCC generates instruction that assembler rejects mkuvyrkov at gcc dot gnu.org
2024-03-11 17:34 ` [Bug target/114307] " rearnsha at gcc dot gnu.org
@ 2024-03-11 17:35 ` rearnsha at gcc dot gnu.org
2024-03-11 21:36 ` [Bug testsuite/114307] " pinskia at gcc dot gnu.org
` (7 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: rearnsha at gcc dot gnu.org @ 2024-03-11 17:35 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114307
--- Comment #2 from Richard Earnshaw <rearnsha at gcc dot gnu.org> ---
Note that it's clear from the .syntax markers that this is inline assembler
that's the source of the invalid instructions.
^ permalink raw reply [flat|nested] 11+ messages in thread
* [Bug testsuite/114307] [ARM] GCC generates instruction that assembler rejects
2024-03-11 16:13 [Bug target/114307] New: [ARM] GCC generates instruction that assembler rejects mkuvyrkov at gcc dot gnu.org
2024-03-11 17:34 ` [Bug target/114307] " rearnsha at gcc dot gnu.org
2024-03-11 17:35 ` rearnsha at gcc dot gnu.org
@ 2024-03-11 21:36 ` pinskia at gcc dot gnu.org
2024-03-12 14:45 ` mkuvyrkov at gcc dot gnu.org
` (6 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: pinskia at gcc dot gnu.org @ 2024-03-11 21:36 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114307
Andrew Pinski <pinskia at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Target| |arm-linux-gnueabihf
Component|target |testsuite
--- Comment #3 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
From testsuite/gcc.dg/vect/tree-vect.h:
```
{
/* On some processors without NEON support, this instruction may
be a no-op, on others it may trap, so check that it executes
correctly. */
long long a = 0, b = 1;
asm ("vorr %P0, %P1, %P2"
: "=w" (a)
: "0" (a), "w" (b));
if (a != 1)
exit (0);
}
```
Hmm, what is the correct way of testing this here?
Also the other thing is maybe:
/* { dg-do run } */
Should be removed ...
The testcases in vect default to run if it is on HW that supports the SIMD
registers; otherwise it defaults to compile.
The only cases where specifying run is needed is if dg-additional-sources is
used.
Anyways this is a still a testsuite issue either way.
^ permalink raw reply [flat|nested] 11+ messages in thread
* [Bug testsuite/114307] [ARM] GCC generates instruction that assembler rejects
2024-03-11 16:13 [Bug target/114307] New: [ARM] GCC generates instruction that assembler rejects mkuvyrkov at gcc dot gnu.org
` (2 preceding siblings ...)
2024-03-11 21:36 ` [Bug testsuite/114307] " pinskia at gcc dot gnu.org
@ 2024-03-12 14:45 ` mkuvyrkov at gcc dot gnu.org
2024-03-12 16:12 ` [Bug testsuite/114307] [ARM] Vectorization tests not disabled for vector-less targets mkuvyrkov at gcc dot gnu.org
` (5 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: mkuvyrkov at gcc dot gnu.org @ 2024-03-12 14:45 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114307
--- Comment #4 from Maxim Kuvyrkov <mkuvyrkov at gcc dot gnu.org> ---
What I don't understand is why vect.exp tests run at all for 32-bit ARM
non-neon targets.
All vect.exp are predicated on check_vect_support_and_set_flags, which, as far
as I can tell, has only arm_neon_ok clause for 32-bit ARM.
I'm reproducing this problem locally to understand .exp flow. If anyone knows
the answer off-hand -- please share.
Thanks!
^ permalink raw reply [flat|nested] 11+ messages in thread
* [Bug testsuite/114307] [ARM] Vectorization tests not disabled for vector-less targets
2024-03-11 16:13 [Bug target/114307] New: [ARM] GCC generates instruction that assembler rejects mkuvyrkov at gcc dot gnu.org
` (3 preceding siblings ...)
2024-03-12 14:45 ` mkuvyrkov at gcc dot gnu.org
@ 2024-03-12 16:12 ` mkuvyrkov at gcc dot gnu.org
2024-03-12 17:13 ` pinskia at gcc dot gnu.org
` (4 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: mkuvyrkov at gcc dot gnu.org @ 2024-03-12 16:12 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114307
--- Comment #5 from Maxim Kuvyrkov <mkuvyrkov at gcc dot gnu.org> ---
Thanks to Christophe L. for explaining the logic behind "is-effective-target
arm_neon_ok".
The issue is that "/* { dg-options "-O3" } */" in pr113576.c overrides
DEFAULT_VECTFLAGS set by check_vect_support_and_set_flags, which contains
"-mfpu=neon" -- as added by "is-effective-target arm_neon_ok".
It so happens that pr113576.c is the only test that both uses "dg-options" and
"tree-vect.h", thus the new error.
^ permalink raw reply [flat|nested] 11+ messages in thread
* [Bug testsuite/114307] [ARM] Vectorization tests not disabled for vector-less targets
2024-03-11 16:13 [Bug target/114307] New: [ARM] GCC generates instruction that assembler rejects mkuvyrkov at gcc dot gnu.org
` (4 preceding siblings ...)
2024-03-12 16:12 ` [Bug testsuite/114307] [ARM] Vectorization tests not disabled for vector-less targets mkuvyrkov at gcc dot gnu.org
@ 2024-03-12 17:13 ` pinskia at gcc dot gnu.org
2024-03-13 6:24 ` mkuvyrkov at gcc dot gnu.org
` (3 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: pinskia at gcc dot gnu.org @ 2024-03-12 17:13 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114307
--- Comment #6 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
The easiest way to fix this testcase is to rename the testcase to O3-pr113576.c
and remove the dg-options
Though we should audit all of the other ones that use dg-options too:
gimplefe-40.c:/* { dg-options "-fgimple -Wno-psabi -w" } */
gimplefe-41.c:/* { dg-options "-fgimple -Wno-psabi -w" } */
pr101145inf.c:/* { dg-options "-O3" } */
pr101145inf_1.c:/* { dg-options "-O3" } */
pr108316.c:/* { dg-options "-O3" } */
pr84711.c:/* { dg-options "-O2 -Wno-psabi" } */
pr85597.c:/* { dg-options "-O3" } */
pr88497-1.c:/* { dg-options "-O2 -ffast-math -fdump-tree-reassoc1" } */
pr88497-2.c:/* { dg-options "-O2 -ffast-math -fdump-tree-reassoc1" } */
pr88497-3.c:/* { dg-options "-O2 -ffast-math -fdump-tree-reassoc1" } */
pr88497-4.c:/* { dg-options "-O2 -ffast-math -fdump-tree-reassoc1" } */
pr88497-5.c:/* { dg-options "-O2 -ffast-math -fdump-tree-reassoc1" } */
pr88497-6.c:/* { dg-options "-O2 -mavx512f -ffast-math -fdump-tree-reassoc1" }
*/
pr88497-7.c:/* { dg-options "-O2 -mavx512f -ffast-math -fdump-tree-reassoc1" }
*/
pr92347.c:/* { dg-options "-O1 -fopenmp-simd" } */
pr93069.c:/* { dg-options "-O2 -fopenmp-simd" } */
pr97241.c:/* { dg-options "-O3 --param max-loop-header-insns=2" } */
pr99102.c:/* { dg-options "-O2 -ftree-vectorize -fno-vect-cost-model
-fdump-tree-vect-details" } */
vect-fold-1.c:/* { dg-options "-O2 -fdump-tree-ccp1" } */
vect-reduc-epilogue-gaps.c:/* { dg-options "-O3 -fno-vect-cost-model" } */
vect-singleton_1.c:/* { dg-options "-Warray-bounds -O2 -fno-inline -std=c99" }
*/
Use dg-additional-options instead and/or rename if needed.
^ permalink raw reply [flat|nested] 11+ messages in thread
* [Bug testsuite/114307] [ARM] Vectorization tests not disabled for vector-less targets
2024-03-11 16:13 [Bug target/114307] New: [ARM] GCC generates instruction that assembler rejects mkuvyrkov at gcc dot gnu.org
` (5 preceding siblings ...)
2024-03-12 17:13 ` pinskia at gcc dot gnu.org
@ 2024-03-13 6:24 ` mkuvyrkov at gcc dot gnu.org
2024-03-13 11:03 ` mkuvyrkov at gcc dot gnu.org
` (2 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: mkuvyrkov at gcc dot gnu.org @ 2024-03-13 6:24 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114307
Maxim Kuvyrkov <mkuvyrkov at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Assignee|unassigned at gcc dot gnu.org |mkuvyrkov at gcc dot gnu.org
--- Comment #7 from Maxim Kuvyrkov <mkuvyrkov at gcc dot gnu.org> ---
Working on this, including reviewing gcc.dg/vect/, g++.dg/vect/ and
gfortran.dg/vect/ testsuites.
^ permalink raw reply [flat|nested] 11+ messages in thread
* [Bug testsuite/114307] [ARM] Vectorization tests not disabled for vector-less targets
2024-03-11 16:13 [Bug target/114307] New: [ARM] GCC generates instruction that assembler rejects mkuvyrkov at gcc dot gnu.org
` (6 preceding siblings ...)
2024-03-13 6:24 ` mkuvyrkov at gcc dot gnu.org
@ 2024-03-13 11:03 ` mkuvyrkov at gcc dot gnu.org
2024-03-28 13:44 ` cvs-commit at gcc dot gnu.org
2024-03-28 13:50 ` mkuvyrkov at gcc dot gnu.org
9 siblings, 0 replies; 11+ messages in thread
From: mkuvyrkov at gcc dot gnu.org @ 2024-03-13 11:03 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114307
--- Comment #8 from Maxim Kuvyrkov <mkuvyrkov at gcc dot gnu.org> ---
Patch posted:
https://patchwork.sourceware.org/project/gcc/patch/20240313105839.2785627-1-maxim.kuvyrkov@linaro.org/
^ permalink raw reply [flat|nested] 11+ messages in thread
* [Bug testsuite/114307] [ARM] Vectorization tests not disabled for vector-less targets
2024-03-11 16:13 [Bug target/114307] New: [ARM] GCC generates instruction that assembler rejects mkuvyrkov at gcc dot gnu.org
` (7 preceding siblings ...)
2024-03-13 11:03 ` mkuvyrkov at gcc dot gnu.org
@ 2024-03-28 13:44 ` cvs-commit at gcc dot gnu.org
2024-03-28 13:50 ` mkuvyrkov at gcc dot gnu.org
9 siblings, 0 replies; 11+ messages in thread
From: cvs-commit at gcc dot gnu.org @ 2024-03-28 13:44 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114307
--- Comment #9 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Maxim Kuvyrkov <mkuvyrkov@gcc.gnu.org>:
https://gcc.gnu.org/g:b8e7aaaf350a4584d9b76e8dd69daa2203bac339
commit r14-9706-gb8e7aaaf350a4584d9b76e8dd69daa2203bac339
Author: Maxim Kuvyrkov <maxim.kuvyrkov@linaro.org>
Date: Wed Mar 13 06:48:47 2024 +0000
[testsuite] Fixup dg-options in {gcc,g++,gfortran}.dg/vect.exp tests
Testsuites driven by vect.exp rely on check_vect_support_and_set_flags
to set appropriate DEFAULT_VECTFLAGS for a given target (e.g., add
-mfpu=neon for arm-linux-gnueabi). Unfortunately, these flags are
overwritten by dg-options directive, which can cause tests to fail.
Behavior of dg-options is documented in vect.exp files, but not
all developers look at the .exp file when adding a new testcase.
This caused a few dg-options directives to be used instead of
the more appropriate dg-additional-options.
This patch changes target-independent dg-options into
dg-additional-options. This patch does not touch target-specific
dg-options and target-specific tests to avoid disturbing the gentle
balance of target-specific vectorization.
This patch also removes a couple of unneeded "dg-do run" directives
to avoid failures on compile-only targets. Default action is, again,
set by check_vect_support_and_set_flags.
Lastly, I avoided renaming tests that use -O<n> options to O<n>-*
filename format because this support is not consistent between
gcc.dg/vect/, g++.dg/vect/, and gfortran.dg/vect/ testsuites.
It seems dg-additional-options is cleaner.
This patch does the following,
1. do not change target-specific tests, e.g.,
gcc.dg/vect/costmodel/riscv/*;
2. do not change { dg-options FOO { target { target-*-pattern } } };
3. do not remove { dg-do run { target { target-*-pattern } } };
4. change { dg-options FOO } to { dg-additional-options FOO };
5. remove { dg-do run } in several tests, where it is clearly not needed.
gcc/testsuite/ChangeLog:
PR testsuite/114307
* gcc.dg/vect/vect-cond-reduc-in-order-2-signed-zero.c: Remove
dg-run.
* gcc.dg/vect/complex/complex-operations-run.c: Likewise.
* gcc.dg/vect/pr113576.c: Remove dg-run. Use dg-additional-options
for
test-specific flags.
* gcc.dg/vect/gimplefe-40.c: Use dg-additional-options for
test-specific flags.
* gcc.dg/vect/gimplefe-41.c: Likewise.
* gcc.dg/vect/pr101145inf.c: Likewise.
* gcc.dg/vect/pr101145inf_1.c: Likewise.
* gcc.dg/vect/pr108316.c: Likewise.
* gcc.dg/vect/pr109011-1.c: Likewise.
* gcc.dg/vect/pr109011-2.c: Likewise.
* gcc.dg/vect/pr109011-3.c: Likewise.
* gcc.dg/vect/pr109011-4.c: Likewise.
* gcc.dg/vect/pr109011-5.c: Likewise.
* gcc.dg/vect/pr111846.c: Likewise.
* gcc.dg/vect/pr111860-2.c: Likewise.
* gcc.dg/vect/pr111860-3.c: Likewise.
* gcc.dg/vect/pr113002.c: Likewise.
* gcc.dg/vect/pr84711.c: Likewise.
* gcc.dg/vect/pr85597.c: Likewise.
* gcc.dg/vect/pr88497-1.c: Likewise.
* gcc.dg/vect/pr88497-2.c: Likewise.
* gcc.dg/vect/pr88497-3.c: Likewise.
* gcc.dg/vect/pr88497-4.c: Likewise.
* gcc.dg/vect/pr88497-5.c: Likewise.
* gcc.dg/vect/pr88497-7.c: Likewise.
* gcc.dg/vect/pr92347.c: Likewise.
* gcc.dg/vect/pr93069.c: Likewise.
* gcc.dg/vect/pr97241.c: Likewise.
* gcc.dg/vect/pr99102.c: Likewise.
* gcc.dg/vect/vect-early-break_65.c: Likewise.
* gcc.dg/vect/vect-fold-1.c: Likewise.
* gcc.dg/vect/vect-ifcvt-19.c: Likewise.
* gcc.dg/vect/vect-ifcvt-20.c: Likewise.
* gcc.dg/vect/vect-reduc-epilogue-gaps.c: Likewise.
* gcc.dg/vect/vect-singleton_1.c: Likewise.
* g++.dg/vect/pr84556.cc: Likewise.
* gfortran.dg/vect/fast-math-mgrid-resid.f: Likewise.
* gfortran.dg/vect/pr77848.f: Likewise.
* gfortran.dg/vect/pr90913.f90: Likewise.
^ permalink raw reply [flat|nested] 11+ messages in thread
* [Bug testsuite/114307] [ARM] Vectorization tests not disabled for vector-less targets
2024-03-11 16:13 [Bug target/114307] New: [ARM] GCC generates instruction that assembler rejects mkuvyrkov at gcc dot gnu.org
` (8 preceding siblings ...)
2024-03-28 13:44 ` cvs-commit at gcc dot gnu.org
@ 2024-03-28 13:50 ` mkuvyrkov at gcc dot gnu.org
9 siblings, 0 replies; 11+ messages in thread
From: mkuvyrkov at gcc dot gnu.org @ 2024-03-28 13:50 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114307
Maxim Kuvyrkov <mkuvyrkov at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Resolution|--- |FIXED
Status|NEW |RESOLVED
--- Comment #10 from Maxim Kuvyrkov <mkuvyrkov at gcc dot gnu.org> ---
Fixed.
^ permalink raw reply [flat|nested] 11+ messages in thread
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