[Bug c/114352] New: RISC-V: ICE when __attribute__((target("arch=+v")) and build with rv64gc -O3

[Bug c/114352] New: RISC-V: ICE when __attribute__((target("arch=+v")) and build with rv64gc -O3

[pan2.li at intel dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114352

            Bug ID: 114352
           Summary: RISC-V: ICE when __attribute__((target("arch=+v")) and
                    build with rv64gc -O3
           Product: gcc
           Version: 14.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: c
          Assignee: unassigned at gcc dot gnu.org
          Reporter: pan2.li at intel dot com
  Target Milestone: ---

Assume we have a sample code as below

void
__attribute__((target("arch=+v")))
add (int *a, int *b, int *out, unsigned count)
{
  unsigned i;

  for (i = 0; i < count; i++)
    out[i] = a[i] + b[i];
}

When build with -march=rv64gc -O3 there will be ICE as below:
test.c: In function ‘add’:
test.c:4:1: internal compiler error: Floating point exception                  
                                                                               
                                                     4 | {
      | ^                                                                      
                                                                               
                                                 0x1a5891b crash_signal        
                                                                               
                                                                               
                         
/home/pli/gcc/333/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/toplev.cc:319
                                                                               
                                         0x7f0a7884251f ???
        ./signal/../sysdeps/unix/sysv/linux/x86_64/libc_sigaction.c:0
0x1f51ba4 riscv_hard_regno_nregs
       
/home/pli/gcc/333/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/config/riscv/riscv.cc:8143
0x1967bb9 init_reg_modes_target()
       
/home/pli/gcc/333/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/reginfo.cc:471
0x13fc029 init_emit_regs()
       
/home/pli/gcc/333/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/emit-rtl.cc:6237
0x1a5b83d target_reinit()
       
/home/pli/gcc/333/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/toplev.cc:1936
0x35e374d save_target_globals()
       
/home/pli/gcc/333/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/target-globals.cc:92
0x35e381f save_target_globals_default_opts()
       
/home/pli/gcc/333/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/target-globals.cc:122
0x1f544cc riscv_save_restore_target_globals(tree_node*)
       
/home/pli/gcc/333/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/config/riscv/riscv.cc:9138
0x1f55c36 riscv_set_current_function
       
/home/pli/gcc/333/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/config/riscv/riscv.cc:9477
0x1505be7 invoke_set_current_function_hook
       
/home/pli/gcc/333/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/function.cc:4690
0x1505f60 allocate_struct_function(tree_node*, bool)
       
/home/pli/gcc/333/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/function.cc:4813
0x1044e33 store_parm_decls()
       
/home/pli/gcc/333/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/c/c-decl.cc:11084
0x10b8a54 c_parser_declaration_or_fndef
       
/home/pli/gcc/333/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/c/c-parser.cc:2975
0x10b62b7 c_parser_external_declaration
       
/home/pli/gcc/333/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/c/c-parser.cc:2046
                                                                               
                                    0x10b5d2a c_parser_translation_unit
       
/home/pli/gcc/333/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/c/c-parser.cc:1900
0x110d5f4 c_parse_file()
       
/home/pli/gcc/333/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/c/c-parser.cc:26889
0x11bd3f3 c_common_parse_file()

Prepare a script for most vector arch combinations we will have:
arch=+v Fail
arch=+zve32x Fail
arch=+zve32f Fail
arch=+zve64x Fail
arch=+zve64f Fail
arch=+zve64d Fail
arch=+zvl64b Pass
arch=+zvl128b Pass
arch=+zvl256b Pass
arch=+zvl4096b Pass
arch=+zve32x_zvl64b Fail
arch=+zve32x_zvl128b Fail
arch=+zve32x_zvl256b Fail
arch=+zve32x_zvl4096b Fail
arch=+zve32f_zvl64b Fail
arch=+zve32f_zvl128b Fail
arch=+zve32f_zvl256b Fail
arch=+zve32f_zvl4096b Fail
arch=+zve64x_zvl64b Fail
arch=+zve64x_zvl128b Fail
arch=+zve64x_zvl256b Fail
arch=+zve64x_zvl4096b Fail
arch=+zve64f_zvl64b Fail
arch=+zve64f_zvl128b Fail
arch=+zve64f_zvl256b Fail
arch=+zve64f_zvl4096b Fail
arch=+zve64d_zvl64b Fail
arch=+zve64d_zvl128b Fail
arch=+zve64d_zvl256b Fail
arch=+zve64d_zvl4096b Fail

The passed arch cannot vectorized but the -march=armv8-a -O3 with
__attribute__((target("+sve2"))) can vectorize.

I will try to fix this ICE soon.

[Bug c/114352] RISC-V: ICE when __attribute__((target("arch=+v")) and build with rv64gc -O3

[pan2.li at intel dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114352

--- Comment #1 from Li Pan <pan2.li at intel dot com> ---
Test GCC version:

riscv64-unknown-elf-gcc (GCC) 14.0.1 20240315 (experimental)
Copyright (C) 2024 Free Software Foundation, Inc.
This is free software; see the source for copying conditions.  There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

[Bug target/114352] RISC-V: ICE when __attribute__((target("arch=+v")) and build with rv64gc -O3

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114352

--- Comment #2 from Richard Biener <rguenth at gcc dot gnu.org> ---
*** Bug 114351 has been marked as a duplicate of this bug. ***

[Bug target/114352] RISC-V: ICE when __attribute__((target("arch=+v")) and build with rv64gc -O3

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114352

--- Comment #3 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Pan Li <panli@gcc.gnu.org>:

https://gcc.gnu.org/g:d3c24e9e55a7cf18df313a8b32b6de4b3ba81013

commit r14-9604-gd3c24e9e55a7cf18df313a8b32b6de4b3ba81013
Author: Pan Li <pan2.li@intel.com>
Date:   Mon Mar 18 11:21:29 2024 +0800

    RISC-V: Bugfix ICE for __attribute__((target("arch=+v"))

    This patch would like to fix one ICE for __attribute__((target("arch=+v"))
    and likewise extension(s). Given we have sample code as below:

    void __attribute__((target("arch=+v")))
    test_2 (int *a, int *b, int *out, unsigned count)
    {
      unsigned i;
      for (i = 0; i < count; i++)
       out[i] = a[i] + b[i];
    }

    It will have ICE when build with -march=rv64gc -O3.

    test.c: In function âtest_2â:
    test.c:4:1: internal compiler error: Floating point exception
    4 | {
          | ^
    0x1a5891b crash_signal
    .../__RISC-V_BUILD__/../gcc/toplev.cc:319
    0x7f0a7884251f ???
            ./signal/../sysdeps/unix/sysv/linux/x86_64/libc_sigaction.c:0
    0x1f51ba4 riscv_hard_regno_nregs
            .../__RISC-V_BUILD__/../gcc/config/riscv/riscv.cc:8143
    0x1967bb9 init_reg_modes_target()
            .../__RISC-V_BUILD__/../gcc/reginfo.cc:471
    0x13fc029 init_emit_regs()
            .../__RISC-V_BUILD__/../gcc/emit-rtl.cc:6237
    0x1a5b83d target_reinit()
            .../__RISC-V_BUILD__/../gcc/toplev.cc:1936
    0x35e374d save_target_globals()
            .../__RISC-V_BUILD__/../gcc/target-globals.cc:92
    0x35e381f save_target_globals_default_opts()
            .../__RISC-V_BUILD__/../gcc/target-globals.cc:122
    0x1f544cc riscv_save_restore_target_globals(tree_node*)
            .../__RISC-V_BUILD__/../gcc/config/riscv/riscv.cc:9138
    0x1f55c36 riscv_set_current_function
    ...

    There are two reasons for this ICE.
    1. The implied extension(s) of v are not well handled and the
       TARGET_MIN_VLEN is 0 which is not reinitialized.  Then the
       size / TARGET_MIN_VLEN will have DivideByZero.
    2. The machine modes of the vector types will be vary after
       the v extension is introduced.

    This patch passed below testsuite:
    1. The riscv fully regression test.

            PR target/114352

    gcc/ChangeLog:

            * common/config/riscv/riscv-common.cc (riscv_subset_list::parse):
            Replace implied, combine and check to func finalize.
            (riscv_subset_list::finalize): New func impl to take care of
            implied, combine ext and related checks.
            * config/riscv/riscv-subset.h: Add func decl for finalize.
            * config/riscv/riscv-target-attr.cc
(riscv_target_attr_parser::parse_arch):
            Finalize the ext before return succeed.
            * config/riscv/riscv.cc (riscv_set_current_function): Reinit the
            machine mode before when set cur function.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/base/pr114352-1.c: New test.
            * gcc.target/riscv/rvv/base/pr114352-2.c: New test.

    Signed-off-by: Pan Li <pan2.li@intel.com>

[Bug target/114352] RISC-V: ICE when __attribute__((target("arch=+v")) and build with rv64gc -O3

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114352

--- Comment #4 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Pan Li <panli@gcc.gnu.org>:

https://gcc.gnu.org/g:9941f0295a14659e25260458efd2e46a68ad0342

commit r14-9605-g9941f0295a14659e25260458efd2e46a68ad0342
Author: Pan Li <pan2.li@intel.com>
Date:   Tue Mar 19 09:43:24 2024 +0800

    RISC-V: Bugfix function target attribute pollution

    This patch depends on below ICE fix.

    https://gcc.gnu.org/pipermail/gcc-patches/2024-March/647915.html

    The function target attribute should be on a per-function basis.
    For example, we have 3 function as below:

    void test_1 () {}

    void __attribute__((target("arch=+v"))) test_2 () {}

    void __attribute__((target("arch=+zfh"))) test_3 () {}

    void test_4 () {}

    The scope of the target attribute should not extend the function body.
    Aka, test_3 cannot have the 'v' extension, as well as the test_4
    cannot have both the 'v' and 'zfh' extension.

    Unfortunately, for now the test_4 is able to leverage the 'v' and
    the 'zfh' extension which is incorrect.  This patch would like to
    fix the sticking attribute by introduce the commandline subset_list.
    When parse_arch, we always clone from the cmdline_subset_list instead
    of the current_subset_list.

    Meanwhile, we correct the print information about arch like below.

    .option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zbb1p0

    The riscv_declare_function_name hook is always after the hook
    riscv_process_target_attr.  Thus, we introduce one hash_map to record
    the 1:1 mapping from fndel to its' subset_list in advance.  And later
    the riscv_declare_function_name is able to get the right information
    about the arch.

    Below test are passed for this patch
    * The riscv fully regression test.

            PR target/114352

    gcc/ChangeLog:

            * common/config/riscv/riscv-common.cc (struct
riscv_func_target_info):
            New struct for func decl and target name.
            (struct riscv_func_target_hasher): New hasher for hash table
mapping
            from the fn_decl to fn_target_name.
            (riscv_func_decl_hash): New func to compute the hash for fn_decl.
            (riscv_func_target_hasher::hash): New func to impl hash interface.
            (riscv_func_target_hasher::equal): New func to impl equal
interface.
            (riscv_cmdline_subset_list): New static var for cmdline subset
list.
            (riscv_func_target_table_lazy_init): New func to lazy init the func
            target hash table.
            (riscv_func_target_get): New func to get target name from hash
table.
            (riscv_func_target_put): New func to put target name into hash
table.
            (riscv_func_target_remove_and_destory): New func to remove target
            info from the hash table and destory it.
            (riscv_parse_arch_string): Set the static var cmdline_subset_list.
            * config/riscv/riscv-subset.h (riscv_cmdline_subset_list): New
static
            var for cmdline subset list.
            (riscv_func_target_get): New func decl.
            (riscv_func_target_put): Ditto.
            (riscv_func_target_remove_and_destory): Ditto.
            * config/riscv/riscv-target-attr.cc
(riscv_target_attr_parser::parse_arch):
            Take cmdline_subset_list instead of current_subset_list when clone.
            (riscv_process_target_attr): Record the func target info to hash
table.
            (riscv_option_valid_attribute_p): Add new arg tree fndel.
            * config/riscv/riscv.cc (riscv_declare_function_name): Consume the
            func target info and print the arch message.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/base/pr114352-3.c: New test.

    Signed-off-by: Pan Li <pan2.li@intel.com>

[Bug target/114352] RISC-V: ICE when __attribute__((target("arch=+v")) and build with rv64gc -O3

[pan2.li at intel dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114352

Li Pan <pan2.li at intel dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
         Resolution|---                         |FIXED
             Status|UNCONFIRMED                 |RESOLVED

--- Comment #5 from Li Pan <pan2.li at intel dot com> ---
Fixed.