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From: "pan2.li at intel dot com" <gcc-bugzilla@gcc.gnu.org> To: gcc-bugs@gcc.gnu.org Subject: [Bug target/114639] [riscv] ICE in create_pre_exit, at mode-switching.cc:451 Date: Tue, 09 Apr 2024 15:30:41 +0000 [thread overview] Message-ID: <bug-114639-4-4duzHoQ4P5@http.gcc.gnu.org/bugzilla/> (raw) In-Reply-To: <bug-114639-4@http.gcc.gnu.org/bugzilla/> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114639 --- Comment #12 from Li Pan <pan2.li at intel dot com> --- #include <riscv_vector.h> extern unsigned long get_vl (); #if 0 #else vint32m1_t test (vint32m1_t a) { unsigned b; return __riscv_vadd_vx_i32m1 (a, b, get_vl ()); // No ICE } vbool16_t test (vuint64m4_t a) { unsigned long b; return __riscv_vmsne_vx_u64m4_b16 (a, b, get_vl ()); // ICE } #endif This is comes from the below parts: !(targetm.class_likely_spilled_p (REGNO_REG_CLASS (ret_start))); For RVV, the reg_class values are listed as below. Because the Vector Mask has only one reg, then it will be considered as likely spilled as the hook TARGET_CLASS_LIKELY_SPILLED_P default returns true if reg_class_size[class] == 1. Not very sure if overriding TARGET_CLASS_LIKELY_SPILLED_P hook for riscv is a reasonable fix, trying to understand TARGET_CLASS_LIKELY_SPILLED_P... --------panli-----reg_class_size[0]=0 --------panli-----reg_class_size[1]=14 --------panli-----reg_class_size[2]=26 --------panli-----reg_class_size[3]=32 --------panli-----reg_class_size[4]=32 --------panli-----reg_class_size[5]=2 --------panli-----reg_class_size[6]=1 <= VM --------panli-----reg_class_size[7]=31 <= VD --------panli-----reg_class_size[8]=32 <= V --------panli-----reg_class_size[9]=98
next prev parent reply other threads:[~2024-04-09 15:30 UTC|newest] Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-04-08 12:29 [Bug target/114639] New: " schwab@linux-m68k.org 2024-04-08 14:08 ` [Bug target/114639] " kito at gcc dot gnu.org 2024-04-08 18:13 ` pinskia at gcc dot gnu.org 2024-04-09 1:26 ` pan2.li at intel dot com 2024-04-09 1:28 ` kito at gcc dot gnu.org 2024-04-09 1:33 ` pan2.li at intel dot com 2024-04-09 1:37 ` juzhe.zhong at rivai dot ai 2024-04-09 3:45 ` pan2.li at intel dot com 2024-04-09 7:22 ` pan2.li at intel dot com 2024-04-09 8:05 ` ubizjak at gmail dot com 2024-04-09 8:32 ` pan2.li at intel dot com 2024-04-09 11:55 ` pan2.li at intel dot com 2024-04-09 15:30 ` pan2.li at intel dot com [this message] 2024-04-10 3:20 ` pan2.li at intel dot com 2024-04-11 3:02 ` cvs-commit at gcc dot gnu.org 2024-04-16 8:47 ` schwab@linux-m68k.org 2024-04-22 22:53 ` juzhe.zhong at rivai dot ai 2024-04-28 6:02 ` pan2.li at intel dot com 2024-04-28 6:22 ` juzhe.zhong at rivai dot ai 2024-04-28 6:51 ` pan2.li at intel dot com
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