[Bug target/114714] [RISC-V][RVV] ICE: insn does not satisfy its constraints (postreload)

["pan2.li at intel dot com" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114714

--- Comment #2 from Li Pan <pan2.li at intel dot com> ---
The vzext.vf2 has earlyclobber dest operand, and then it cannot allocated to
the source operand, like vzext.vf2 v0, v0.  Thus we will fail when check_rtl.

(define_insn "@pred_<optab><mode>_vf2"
  [(set (match_operand:VWEXTI 0 "register_operand"                 "=vd, vr,
vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr")
........(if_then_else:VWEXTI
........  (unspec:<VM>
........    [(match_operand:<VM> 1 "vector_mask_operand"           " vm,Wc1,
vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1")
........     (match_operand 4 "vector_length_operand"              " rK, rK,
rK, rK, rK, rK, rK, rK, rK, rK, rK, rK,   rK,   rK")
........     (match_operand 5 "const_int_operand"                  "i,  i,  i, 
i,  i,  i,  i,  i,  i,  i,  i,  i,    i,    i")
........     (match_operand 6 "const_int_operand"                  "i,  i,  i, 
i,  i,  i,  i,  i,  i,  i,  i,  i,    i,    i")
........     (match_operand 7 "const_int_operand"                  "i,  i,  i, 
i,  i,  i,  i,  i,  i,  i,  i,  i,    i,    i")
........     (reg:SI VL_REGNUM)
........     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
........  (any_extend:VWEXTI
........    (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand"  
"W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,   vr,   vr"))
........  (match_operand:VWEXTI 2 "vector_merge_operand"           " vu, vu, 
0,  0, vu, vu,  0,  0, vu, vu,  0,  0,   vu,    0")))]
  "TARGET_VECTOR"
  "v<sz>ext.vf2\t%0,%3%p1"
  [(set_attr "type" "vext")
   (set_attr "mode" "<MODE>")
   (set_attr "group_overlap"
"W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none")])

----------------------------------------------------------------------------------------------------

insn 1205 1214 5405 70 (set (reg:RVVM1SI 97 v1 [orig:687 _1177 ] [687])
        (if_then_else:RVVM1SI (unspec:RVVMF32BI [
                    (const_vector:RVVMF32BI repeat [
                            (const_int 1 [0x1])
                        ])
                    (reg:DI 25 s9 [orig:539 _889 ] [539])
                    (const_int 2 [0x2]) repeated x2
                    (const_int 0 [0])
                    (reg:SI 66 vl)
                    (reg:SI 67 vtype)
                ] UNSPEC_VPREDICATE)
            (zero_extend:RVVM1SI (reg:RVVMF2HI 97 v1 [orig:654 _1100 ] [654]))
            (unspec:RVVM1SI [
                    (reg:DI 0 zero)
                ] UNSPEC_VUNDEF))) "../hwy/ops/rvv-inl.h":1964:386 discrim 1
8452 {pred_zero_extendrvvm1si_vf2}
     (nil))
during RTL pass: reload