[Bug target/114714] [RISC-V][RVV] ICE: insn does not satisfy its constraints (postreload)

["rdapp at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114714

Robin Dapp <rdapp at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |rdapp at gcc dot gnu.org

--- Comment #5 from Robin Dapp <rdapp at gcc dot gnu.org> ---
Did anybody do some further investigation here?  Juzhe messaged me that this PR
is the original reason for the reversal but I don't yet understand why the
register filters don't encompass the full semantics of RVV overlap.

I looked into the test case and what happens is that, in order to determine the
validity of the alternatives, riscv_get_v_regno_alignment is first being called
with an M2 mode.  Our destination is actually a (subreg:RVVM2SI (reg:RVVM4SI
...) 0), though.  I suppose lra/reload check whether a non-subreg destination
also works and hands us a (reg:RVVM4SI ...) as operand[0].  We pass this to
riscv_get_v_regno_alignment which, for an LMUL4 mode, returns 4, thus wrongly
enabling the W42 alternatives.
A W42 alternative permits hard regs % 4 == 2, which causes us to eventually
choose vr2 as destination and source.  Once the constraints are actually
checked we have a mismatch as none of the alternatives work.

Now I'm not at all sure how lra/reload use operand[0] here but this can surely
be found out.  A quick and dirty hack (attached) that checks the insn's
destination mode instead of operand[0]'s mode gets rid of the ICE and doesn't
cause regressions.

I suppose we're too far ahead with the reversal already but I'd really have
preferred more details.  Maybe somebody has had in-depth look but it just
wasn't posted yet?

--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -6034,6 +6034,22 @@ riscv_get_v_regno_alignment (machine_mode mode)
   return lmul;
 }

+int
+riscv_get_dest_alignment (rtx_insn *insn, rtx operand)
+{
+  const_rtx set = 0;
+  if (GET_CODE (PATTERN (insn)) == SET)
+    {
+      set = PATTERN (insn);
+      rtx op = SET_DEST (set);
+      return riscv_get_v_regno_alignment (GET_MODE (op));
+    }
+  else
+    {
+      return riscv_get_v_regno_alignment (GET_MODE (operand));
+    }
+}
+
 /* Define ASM_OUTPUT_OPCODE to do anything special before
    emitting an opcode.  */
 const char *
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index ce1ee6b9c5e..5113daf2ac7 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -550,15 +550,15 @@ (define_attr "group_overlap_valid" "no,yes"
          (const_string "yes")

          (and (eq_attr "group_overlap" "W21")
-             (match_test "riscv_get_v_regno_alignment (GET_MODE (operands[0]))
!= 2"))
+             (match_test "riscv_get_dest_alignment (insn, operands[0]) != 2"))
         (const_string "no")

          (and (eq_attr "group_overlap" "W42")
-             (match_test "riscv_get_v_regno_alignment (GET_MODE (operands[0]))
!= 4"))
+             (match_test "riscv_get_dest_alignment (insn, operands[0]) != 4"))
         (const_string "no")

          (and (eq_attr "group_overlap" "W84")
-             (match_test "riscv_get_v_regno_alignment (GET_MODE (operands[0]))
!= 8"))
+             (match_test "riscv_get_dest_alignment (insn, operands[0]) != 8"))
         (const_string "no")