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* [Bug middle-end/114733] New: [14] Miscompile with -march=rv64gcv -O3 on riscv
@ 2024-04-16 4:30 patrick at rivosinc dot com
2024-04-16 7:44 ` [Bug middle-end/114733] " rdapp at gcc dot gnu.org
` (6 more replies)
0 siblings, 7 replies; 8+ messages in thread
From: patrick at rivosinc dot com @ 2024-04-16 4:30 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114733
Bug ID: 114733
Summary: [14] Miscompile with -march=rv64gcv -O3 on riscv
Product: gcc
Version: 14.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: middle-end
Assignee: unassigned at gcc dot gnu.org
Reporter: patrick at rivosinc dot com
Target Milestone: ---
Testcase:
long b = 1;
signed char c;
int d[25];
int main() {
for (signed char g = 0; g < 8; g += 1)
for (short h = 0; h < 25; h += 2) {
b *= -1;
c ^= d[h];
}
__builtin_printf("%ld\n", b);
}
Commands:
> /scratch/tc-testing/tc-apr-15/build-rv64gcv/bin/riscv64-unknown-linux-gnu-gcc -march=rv64gcv -O3 red.c -o red.out
> /scratch/tc-testing/tc-apr-15/build-rv64gcv/bin/qemu-riscv64 red.out
-1
> /scratch/tc-testing/tc-apr-15/build-rv64gcv/bin/riscv64-unknown-linux-gnu-gcc red.c -o red.out
> /scratch/tc-testing/tc-apr-15/build-rv64gcv/bin/qemu-riscv64 red.out
1
This testcase looks extremely similar to pr114485 so they are likely related -
from my testing pr114485 has NOT regressed.
Tested using r14-9976-gf8409c3109d (not bisected)
Found via fuzzer.
^ permalink raw reply [flat|nested] 8+ messages in thread
* [Bug middle-end/114733] [14] Miscompile with -march=rv64gcv -O3 on riscv
2024-04-16 4:30 [Bug middle-end/114733] New: [14] Miscompile with -march=rv64gcv -O3 on riscv patrick at rivosinc dot com
@ 2024-04-16 7:44 ` rdapp at gcc dot gnu.org
2024-04-16 8:08 ` rguenth at gcc dot gnu.org
` (5 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: rdapp at gcc dot gnu.org @ 2024-04-16 7:44 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114733
--- Comment #1 from Robin Dapp <rdapp at gcc dot gnu.org> ---
Confirmed, also shows up here.
^ permalink raw reply [flat|nested] 8+ messages in thread
* [Bug middle-end/114733] [14] Miscompile with -march=rv64gcv -O3 on riscv
2024-04-16 4:30 [Bug middle-end/114733] New: [14] Miscompile with -march=rv64gcv -O3 on riscv patrick at rivosinc dot com
2024-04-16 7:44 ` [Bug middle-end/114733] " rdapp at gcc dot gnu.org
@ 2024-04-16 8:08 ` rguenth at gcc dot gnu.org
2024-04-16 8:43 ` rguenth at gcc dot gnu.org
` (4 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: rguenth at gcc dot gnu.org @ 2024-04-16 8:08 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114733
Richard Biener <rguenth at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Status|UNCONFIRMED |ASSIGNED
Ever confirmed|0 |1
Assignee|unassigned at gcc dot gnu.org |rguenth at gcc dot gnu.org
--- Comment #2 from Richard Biener <rguenth at gcc dot gnu.org> ---
<bb 2> [local count: 9582068]:
b_lsm.9_16 = b;
_20 = -b_lsm.9_16;
b = _20;
__builtin_printf ("%ld\n", _20);
return 0;
we unroll the inner loop and then vectorize with 8 byte vectors which
means exposing V1DImode vectors which I think runs into the very same
issue (VF is "even").
^ permalink raw reply [flat|nested] 8+ messages in thread
* [Bug middle-end/114733] [14] Miscompile with -march=rv64gcv -O3 on riscv
2024-04-16 4:30 [Bug middle-end/114733] New: [14] Miscompile with -march=rv64gcv -O3 on riscv patrick at rivosinc dot com
2024-04-16 7:44 ` [Bug middle-end/114733] " rdapp at gcc dot gnu.org
2024-04-16 8:08 ` rguenth at gcc dot gnu.org
@ 2024-04-16 8:43 ` rguenth at gcc dot gnu.org
2024-04-16 10:37 ` cvs-commit at gcc dot gnu.org
` (3 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: rguenth at gcc dot gnu.org @ 2024-04-16 8:43 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114733
--- Comment #3 from Richard Biener <rguenth at gcc dot gnu.org> ---
So the issue is that we do
switch (induction_type)
{
case vect_step_op_neg:
if (TREE_CODE (init_expr) != INTEGER_CST
&& TREE_CODE (init_expr) != REAL_CST)
{
/* Check for backend support of NEGATE_EXPR and vec_perm. */
if (!directly_supported_p (NEGATE_EXPR, vectype))
return false;
/* The encoding has 2 interleaved stepped patterns. */
vec_perm_builder sel (nunits, 2, 3);
machine_mode mode = TYPE_MODE (vectype);
sel.quick_grow (6);
for (i = 0; i < 3; i++)
{
sel[i * 2] = i;
sel[i * 2 + 1] = i + nunits;
}
but this scheme doesn't work for a V1DImode vector type.
^ permalink raw reply [flat|nested] 8+ messages in thread
* [Bug middle-end/114733] [14] Miscompile with -march=rv64gcv -O3 on riscv
2024-04-16 4:30 [Bug middle-end/114733] New: [14] Miscompile with -march=rv64gcv -O3 on riscv patrick at rivosinc dot com
` (2 preceding siblings ...)
2024-04-16 8:43 ` rguenth at gcc dot gnu.org
@ 2024-04-16 10:37 ` cvs-commit at gcc dot gnu.org
2024-04-16 10:39 ` [Bug middle-end/114733] [13 Regression] " rguenth at gcc dot gnu.org
` (2 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: cvs-commit at gcc dot gnu.org @ 2024-04-16 10:37 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114733
--- Comment #4 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Richard Biener <rguenth@gcc.gnu.org>:
https://gcc.gnu.org/g:45a41ace55d0ffb1097e374868242329788ec82a
commit r14-9992-g45a41ace55d0ffb1097e374868242329788ec82a
Author: Richard Biener <rguenther@suse.de>
Date: Tue Apr 16 10:46:03 2024 +0200
tree-optimization/114733 - neg induction fails for 1 element vectors
The neg induction vectorization code isn't prepared to deal with
single element vectors.
PR tree-optimization/114733
* tree-vect-loop.cc (vectorizable_nonlinear_induction): Reject
neg induction vectorization of single element vectors.
* gcc.dg/vect/pr114733.c: New testcase.
^ permalink raw reply [flat|nested] 8+ messages in thread
* [Bug middle-end/114733] [13 Regression] Miscompile with -march=rv64gcv -O3 on riscv
2024-04-16 4:30 [Bug middle-end/114733] New: [14] Miscompile with -march=rv64gcv -O3 on riscv patrick at rivosinc dot com
` (3 preceding siblings ...)
2024-04-16 10:37 ` cvs-commit at gcc dot gnu.org
@ 2024-04-16 10:39 ` rguenth at gcc dot gnu.org
2024-05-03 13:55 ` cvs-commit at gcc dot gnu.org
2024-05-03 13:58 ` rguenth at gcc dot gnu.org
6 siblings, 0 replies; 8+ messages in thread
From: rguenth at gcc dot gnu.org @ 2024-04-16 10:39 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114733
Richard Biener <rguenth at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Priority|P3 |P2
Target Milestone|--- |13.3
Summary|[14] Miscompile with |[13 Regression] Miscompile
|-march=rv64gcv -O3 on riscv |with -march=rv64gcv -O3 on
| |riscv
Known to work| |14.0
--- Comment #5 from Richard Biener <rguenth at gcc dot gnu.org> ---
Should be also at least latent on the 13 branch.
^ permalink raw reply [flat|nested] 8+ messages in thread
* [Bug middle-end/114733] [13 Regression] Miscompile with -march=rv64gcv -O3 on riscv
2024-04-16 4:30 [Bug middle-end/114733] New: [14] Miscompile with -march=rv64gcv -O3 on riscv patrick at rivosinc dot com
` (4 preceding siblings ...)
2024-04-16 10:39 ` [Bug middle-end/114733] [13 Regression] " rguenth at gcc dot gnu.org
@ 2024-05-03 13:55 ` cvs-commit at gcc dot gnu.org
2024-05-03 13:58 ` rguenth at gcc dot gnu.org
6 siblings, 0 replies; 8+ messages in thread
From: cvs-commit at gcc dot gnu.org @ 2024-05-03 13:55 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114733
--- Comment #6 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-13 branch has been updated by Richard Biener
<rguenth@gcc.gnu.org>:
https://gcc.gnu.org/g:b3f9f10e03c570074a517dcfe9df8d3eeddd6aca
commit r13-8680-gb3f9f10e03c570074a517dcfe9df8d3eeddd6aca
Author: Richard Biener <rguenther@suse.de>
Date: Tue Apr 16 10:46:03 2024 +0200
tree-optimization/114733 - neg induction fails for 1 element vectors
The neg induction vectorization code isn't prepared to deal with
single element vectors.
PR tree-optimization/114733
* tree-vect-loop.cc (vectorizable_nonlinear_induction): Reject
neg induction vectorization of single element vectors.
* gcc.dg/vect/pr114733.c: New testcase.
(cherry picked from commit 45a41ace55d0ffb1097e374868242329788ec82a)
^ permalink raw reply [flat|nested] 8+ messages in thread
* [Bug middle-end/114733] [13 Regression] Miscompile with -march=rv64gcv -O3 on riscv
2024-04-16 4:30 [Bug middle-end/114733] New: [14] Miscompile with -march=rv64gcv -O3 on riscv patrick at rivosinc dot com
` (5 preceding siblings ...)
2024-05-03 13:55 ` cvs-commit at gcc dot gnu.org
@ 2024-05-03 13:58 ` rguenth at gcc dot gnu.org
6 siblings, 0 replies; 8+ messages in thread
From: rguenth at gcc dot gnu.org @ 2024-05-03 13:58 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114733
Richard Biener <rguenth at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Resolution|--- |FIXED
Known to work| |13.2.1
Known to fail| |13.2.0
Status|ASSIGNED |RESOLVED
--- Comment #7 from Richard Biener <rguenth at gcc dot gnu.org> ---
Fixed.
^ permalink raw reply [flat|nested] 8+ messages in thread
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2024-04-16 4:30 [Bug middle-end/114733] New: [14] Miscompile with -march=rv64gcv -O3 on riscv patrick at rivosinc dot com
2024-04-16 7:44 ` [Bug middle-end/114733] " rdapp at gcc dot gnu.org
2024-04-16 8:08 ` rguenth at gcc dot gnu.org
2024-04-16 8:43 ` rguenth at gcc dot gnu.org
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