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From: "rsaxvc at gmail dot com" <gcc-bugzilla@gcc.gnu.org> To: gcc-bugs@gcc.gnu.org Subject: [Bug target/53938] ARM target generates sub-optimal code (extra instructions) on load from memory Date: Wed, 24 Apr 2024 13:27:56 +0000 [thread overview] Message-ID: <bug-53938-4-tdfWg7vk4L@http.gcc.gnu.org/bugzilla/> (raw) In-Reply-To: <bug-53938-4@http.gcc.gnu.org/bugzilla/> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=53938 --- Comment #6 from rsaxvc at gmail dot com --- This also impacts Cortex-M0 & M23 on GCC13.2.0, just with the new extension instructions. Oddly, when loading a volatile u8 or u16 on Cortex-M3/4/7 does not generate extra zero extension instructions. But these cores do still have separate ldrb/ldrb + sxtab/sxtah sign extension instead of LDRSB/LDRSH.
prev parent reply other threads:[~2024-04-24 13:27 UTC|newest] Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top 2012-07-12 10:58 [Bug target/53938] New: " gregpsmith at live dot co.uk 2012-07-12 11:27 ` [Bug target/53938] " rguenth at gcc dot gnu.org 2012-07-12 16:10 ` pinskia at gcc dot gnu.org 2012-07-12 19:09 ` gregpsmith at live dot co.uk 2013-08-05 21:20 ` rearnsha at gcc dot gnu.org 2024-01-16 22:13 ` pinskia at gcc dot gnu.org 2024-04-24 13:27 ` rsaxvc at gmail dot com [this message]
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