[Bug target/93768] Use vpternlog for composite logical operations

[Bug target/93768] Use vpternlog for composite logical operations

[ak at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=93768

ak at gcc dot gnu.org changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |ak at gcc dot gnu.org
         Resolution|---                         |DUPLICATE
             Status|UNCONFIRMED                 |RESOLVED

--- Comment #2 from ak at gcc dot gnu.org ---
Most of it is already done as part of PR101989

One issue is that it is only for suitable vector types, it doesn't really work
for scalars because the compiler has no idea that a conversion might be
profitable. Perhaps that would be an interesting (but likely) separate feature
to define some frame work to figure out if switching to the vector ISA is worth
it.

*** This bug has been marked as a duplicate of bug 101989 ***

[Bug target/93768] Use vpternlog for composite logical operations

[jbeulich at suse dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=93768

jbeulich at suse dot com changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |jbeulich at suse dot com

--- Comment #3 from jbeulich at suse dot com ---
(In reply to ak from comment #2)
> Most of it is already done as part of PR101989

"Most" really is just one 3rd of what was reported here, isn't it? 101989 is
solely about "Three-input simple logicals" (beyond the small set mentioned
here). In particular I haven't seen gcc do what is requested here as "Two-input
inverted logicals" (I don't think I properly understand the 3rd item about ?:,
as I can't imagine it's meant to apply to a vector of individual bits),
prompting me to start working on some patches. Was marking the report here as
duplicate really appropriate?

[Bug target/93768] Use vpternlog for composite logical operations

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=93768

--- Comment #4 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Jan Beulich <jbeulich@gcc.gnu.org>:

https://gcc.gnu.org/g:607613e516670dd817e7467e774ed2e3440bdb21

commit r14-2309-g607613e516670dd817e7467e774ed2e3440bdb21
Author: Jan Beulich <jbeulich@suse.com>
Date:   Wed Jul 5 09:40:40 2023 +0200

    x86: use VPTERNLOG for further bitwise two-vector operations

    All combinations of and, ior, xor, and not involving two operands can be
    expressed that way in a single insn.

    gcc/

            PR target/93768
            * config/i386/i386.cc (ix86_rtx_costs): Further special-case
            bitwise vector operations.
            * config/i386/sse.md (*iornot<mode>3): New insn.
            (*xnor<mode>3): Likewise.
            (*<nlogic><mode>3): Likewise.
            (andor): New code iterator.
            (nlogic): New code attribute.
            (ternlog_nlogic): Likewise.

    gcc/testsuite/

            PR target/93768
            * gcc.target/i386/avx512-binop-not-1.h: New.
            * gcc.target/i386/avx512-binop-not-2.h: New.
            * gcc.target/i386/avx512f-orn-si-zmm-1.c: New test.
            * gcc.target/i386/avx512f-orn-si-zmm-2.c: New test.

[Bug target/93768] Use vpternlog for composite logical operations

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=93768

--- Comment #5 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Jan Beulich <jbeulich@gcc.gnu.org>:

https://gcc.gnu.org/g:2d11c99dfca3cc603dbbfafb3afc41689a68e40f

commit r14-2310-g2d11c99dfca3cc603dbbfafb3afc41689a68e40f
Author: Jan Beulich <jbeulich@suse.com>
Date:   Wed Jul 5 09:41:09 2023 +0200

    x86: use VPTERNLOG also for certain andnot forms

    When it's the memory operand which is to be inverted, using VPANDN*
    requires a further load instruction. The same can be achieved by a
    single VPTERNLOG*. Add two new alternatives (for plain memory and
    embedded broadcast), adjusting the predicate for the first operand
    accordingly.

    Two pre-existing testcases actually end up being affected (improved) by
    the change, which is reflected in updated expectations there.

    gcc/

            PR target/93768
            * config/i386/sse.md (*andnot<mode>3): Add new alternatives
            for memory form operand 1.

    gcc/testsuite/

            PR target/93768
            * gcc.target/i386/avx512f-andn-di-zmm-2.c: New test.
            * gcc.target/i386/avx512f-andn-si-zmm-2.c: Adjust expecations
            towards generated code.
            * gcc.target/i386/pr100711-3.c: Adjust expectations for 32-bit
            code.