[Bug target/96582] New: aarch64:ICE during GIMPLE pass: veclower

[Bug target/96582] New: aarch64:ICE during GIMPLE pass: veclower

[z.zhanghaijian at huawei dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96582

            Bug ID: 96582
           Summary: aarch64:ICE during GIMPLE pass: veclower
           Product: gcc
           Version: 11.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: z.zhanghaijian at huawei dot com
  Target Milestone: ---

For aarch64 SVE,

The case:
typedef unsigned char v32u8 __attribute__ ((vector_size (32)));

unsigned __attribute__((noinline, noclone))
foo(unsigned u)
{
  v32u8 v32u8_0 = (v32u8){} > (v32u8){-u};
  return v32u8_0[31] + v32u8_0[0];
}

This will cause an ICE when compiled with -S -march=armv8.5-a+sve
-msve-vector-bits=512.

By tracing the debug infomation, It is found that the error is caused by the
failure to find the pattern corresponding to CODE_FOR_vcond_mask_vnx8qivnx8bi.

I tried to extend the mode of this pattern from SVE_FULL to SVE_ALL to fix it.

Proposed patch:
--- a/gcc/config/aarch64/aarch64-sve.md
+++ b/gcc/config/aarch64/aarch64-sve.md
@@ -6722,11 +6722,11 @@ (define_insn "@aarch64_sve_<sve_fp_op><mode>"
 ;; UNSPEC_SEL operand order: mask, true, false (as for VEC_COND_EXPR)
 ;; SEL operand order:        mask, true, false
 (define_expand "@vcond_mask_<mode><vpred>"
-  [(set (match_operand:SVE_FULL 0 "register_operand")
-       (unspec:SVE_FULL
+  [(set (match_operand:SVE_ALL 0 "register_operand")
+       (unspec:SVE_ALL
          [(match_operand:<VPRED> 3 "register_operand")
-          (match_operand:SVE_FULL 1 "aarch64_sve_reg_or_dup_imm")
-          (match_operand:SVE_FULL 2 "aarch64_simd_reg_or_zero")]
+          (match_operand:SVE_ALL 1 "aarch64_sve_reg_or_dup_imm")
+          (match_operand:SVE_ALL 2 "aarch64_simd_reg_or_zero")]
          UNSPEC_SEL))]
   "TARGET_SVE"
   {
@@ -6740,11 +6740,11 @@ (define_expand "@vcond_mask_<mode><vpred>"
 ;; - a duplicated immediate and a register
 ;; - a duplicated immediate and zero
 (define_insn "*vcond_mask_<mode><vpred>"
-  [(set (match_operand:SVE_FULL 0 "register_operand" "=w, w, w, w, ?w, ?&w,
?&w")
-       (unspec:SVE_FULL
+  [(set (match_operand:SVE_ALL 0 "register_operand" "=w, w, w, w, ?w, ?&w,
?&w")
+       (unspec:SVE_ALL
          [(match_operand:<VPRED> 3 "register_operand" "Upa, Upa, Upa, Upa,
Upl, Upl, Upl")
-          (match_operand:SVE_FULL 1 "aarch64_sve_reg_or_dup_imm" "w, vss, vss,
Ufc, Ufc, vss, Ufc")
-          (match_operand:SVE_FULL 2 "aarch64_simd_reg_or_zero" "w, 0, Dz, 0,
Dz, w, w")]
+          (match_operand:SVE_ALL 1 "aarch64_sve_reg_or_dup_imm" "w, vss, vss,
Ufc, Ufc, vss, Ufc")
+          (match_operand:SVE_ALL 2 "aarch64_simd_reg_or_zero" "w, 0, Dz, 0,
Dz, w, w")]
          UNSPEC_SEL))]
   "TARGET_SVE
    && (!register_operand (operands[1], <MODE>mode)

Any suggestions?

[Bug target/96582] aarch64:ICE during GIMPLE pass: veclower

[rsandifo at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96582

rsandifo at gcc dot gnu.org <rsandifo at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |rsandifo at gcc dot gnu.org
             Status|UNCONFIRMED                 |NEW
     Ever confirmed|0                           |1
   Last reconfirmed|                            |2020-08-12

--- Comment #1 from rsandifo at gcc dot gnu.org <rsandifo at gcc dot gnu.org> ---
We shouldn't need to change the patterns for correctness.  I think
this is a bug in tree-vect-generic, which seems to be using the
byte size * 8 instead of the actual bit precision when generating
the BIT_FIELD_REFs.  This sounds similar to PR94980.

See also PR96366#c1 for more about the SVE_FULL stuff.

[Bug target/96582] aarch64:ICE during GIMPLE pass: veclower

[rsandifo at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96582

--- Comment #2 from rsandifo at gcc dot gnu.org <rsandifo at gcc dot gnu.org> ---
*** Bug 96581 has been marked as a duplicate of this bug. ***

[Bug target/96582] aarch64:ICE during GIMPLE pass: veclower

[ktkachov at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96582

ktkachov at gcc dot gnu.org changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |ktkachov at gcc dot gnu.org

--- Comment #3 from ktkachov at gcc dot gnu.org ---
I don't see it ICEing with recent trunk anymore. Can this be closed?

[Bug target/96582] aarch64:ICE during GIMPLE pass: veclower

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96582

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|NEW                         |RESOLVED
         Resolution|---                         |FIXED

--- Comment #4 from Richard Biener <rguenth at gcc dot gnu.org> ---
I guess so.

[Bug target/96582] aarch64:ICE during GIMPLE pass: veclower

[acoplan at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96582

Alex Coplan <acoplan at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |acoplan at gcc dot gnu.org

--- Comment #5 from Alex Coplan <acoplan at gcc dot gnu.org> ---
FWIW, the ICE was "fixed" with
r11-4912-g46c705e70e078f6a1920d92e49042125d5e18495:

commit 46c705e70e078f6a1920d92e49042125d5e18495
Author: Richard Sandiford <richard.sandiford@arm.com>
Date:   Wed Nov 11 11:42:46 2020 +0000

    aarch64: Support SVE comparisons for unpacked integers

    This patch adds support for comparing unpacked SVE integer vectors,
    such as byte elements stored in the bottom bytes of halfword
    containers.  It also adds support for selects between unpacked
    SVE vectors (both integer and floating-point), since selects and
    compares are closely tied via the vcond optab interface.

so not sure if the issue was really fixed or perhaps just hidden.

[Bug target/96582] aarch64:ICE during GIMPLE pass: veclower

[rsandifo at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96582

--- Comment #6 from rsandifo at gcc dot gnu.org <rsandifo at gcc dot gnu.org> ---
(In reply to Alex Coplan from comment #5)
> so not sure if the issue was really fixed or perhaps just hidden.
Yeah, agree it's probably just gone latent.