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* [Bug target/98532] New: Use load/store pairs for 2-element vector in memory permutes
@ 2021-01-05 14:08 ktkachov at gcc dot gnu.org
2021-01-06 8:43 ` [Bug target/98532] " rguenth at gcc dot gnu.org
` (4 more replies)
0 siblings, 5 replies; 6+ messages in thread
From: ktkachov at gcc dot gnu.org @ 2021-01-05 14:08 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98532
Bug ID: 98532
Summary: Use load/store pairs for 2-element vector in memory
permutes
Product: gcc
Version: unknown
Status: UNCONFIRMED
Keywords: missed-optimization
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: ktkachov at gcc dot gnu.org
Target Milestone: ---
Target: aarch64
I've seen these patterns while looking at some disassemblies but I believe it
can be reproduced in C with:
typedef long v2di __attribute__((vector_size (16)));
void
foo (v2di *a, v2di *b)
{
v2di tmp = {(*a)[1], (*a)[0]};
*b = tmp;
}
This, for aarch64 -O2 generates:
foo:
ldr d0, [x0, 8]
ld1 {v0.d}[1], [x0]
str q0, [x1]
ret
clang does:
foo: // @foo
ldr q0, [x0]
ext v0.16b, v0.16b, v0.16b, #8
str q0, [x1]
ret
I suspect we can do better in these cases with:
ldp x2, x3, [x0]
stp x3, x2, [x1]
or something similar.
In the combine phase we already try and fail to match:
Failed to match this instruction:
(set (reg:V2DI 97 [ tmp ])
(vec_concat:V2DI (mem/j:DI (plus:DI (reg/v/f:DI 95 [ a ])
(const_int 8 [0x8])) [1 BIT_FIELD_REF <*a_4(D), 64, 64>+0 S8
A64])
(mem/j:DI (reg/v/f:DI 95 [ a ]) [1 BIT_FIELD_REF <*a_4(D), 64, 0>+0 S8
A128])))
so maybe we can solve this purely in the backend?
^ permalink raw reply [flat|nested] 6+ messages in thread
* [Bug target/98532] Use load/store pairs for 2-element vector in memory permutes
2021-01-05 14:08 [Bug target/98532] New: Use load/store pairs for 2-element vector in memory permutes ktkachov at gcc dot gnu.org
@ 2021-01-06 8:43 ` rguenth at gcc dot gnu.org
2021-02-08 2:32 ` pinskia at gcc dot gnu.org
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: rguenth at gcc dot gnu.org @ 2021-01-06 8:43 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98532
--- Comment #1 from Richard Biener <rguenth at gcc dot gnu.org> ---
_1 = BIT_FIELD_REF <*a_4(D), 64, 64>;
_2 = BIT_FIELD_REF <*a_4(D), 64, 0>;
tmp_5 = {_1, _2};
note this is another case where we'd like to improve forwprop to canonicalize
this to
_1 = *a_4(D);
tmp_5 = VEC_PERM <_1, _1, { 1, 0 }>;
which is more "SSA friendly". That would lead to what clang generates
I guess (and be maybe easier to combine from to ldp/stp).
^ permalink raw reply [flat|nested] 6+ messages in thread
* [Bug target/98532] Use load/store pairs for 2-element vector in memory permutes
2021-01-05 14:08 [Bug target/98532] New: Use load/store pairs for 2-element vector in memory permutes ktkachov at gcc dot gnu.org
2021-01-06 8:43 ` [Bug target/98532] " rguenth at gcc dot gnu.org
@ 2021-02-08 2:32 ` pinskia at gcc dot gnu.org
2021-02-08 4:40 ` pinskia at gcc dot gnu.org
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: pinskia at gcc dot gnu.org @ 2021-02-08 2:32 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98532
Andrew Pinski <pinskia at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Severity|normal |enhancement
CC| |pinskia at gcc dot gnu.org
^ permalink raw reply [flat|nested] 6+ messages in thread
* [Bug target/98532] Use load/store pairs for 2-element vector in memory permutes
2021-01-05 14:08 [Bug target/98532] New: Use load/store pairs for 2-element vector in memory permutes ktkachov at gcc dot gnu.org
2021-01-06 8:43 ` [Bug target/98532] " rguenth at gcc dot gnu.org
2021-02-08 2:32 ` pinskia at gcc dot gnu.org
@ 2021-02-08 4:40 ` pinskia at gcc dot gnu.org
2023-05-12 5:34 ` pinskia at gcc dot gnu.org
2024-02-27 8:27 ` pinskia at gcc dot gnu.org
4 siblings, 0 replies; 6+ messages in thread
From: pinskia at gcc dot gnu.org @ 2021-02-08 4:40 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98532
Andrew Pinski <pinskia at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Last reconfirmed| |2021-02-08
Status|UNCONFIRMED |ASSIGNED
Assignee|unassigned at gcc dot gnu.org |pinskia at gcc dot gnu.org
Ever confirmed|0 |1
--- Comment #2 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Related to PR 93237.
I am going to fix this for GCC 12. I have a few patches which already improve
this ....
^ permalink raw reply [flat|nested] 6+ messages in thread
* [Bug target/98532] Use load/store pairs for 2-element vector in memory permutes
2021-01-05 14:08 [Bug target/98532] New: Use load/store pairs for 2-element vector in memory permutes ktkachov at gcc dot gnu.org
` (2 preceding siblings ...)
2021-02-08 4:40 ` pinskia at gcc dot gnu.org
@ 2023-05-12 5:34 ` pinskia at gcc dot gnu.org
2024-02-27 8:27 ` pinskia at gcc dot gnu.org
4 siblings, 0 replies; 6+ messages in thread
From: pinskia at gcc dot gnu.org @ 2023-05-12 5:34 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98532
Andrew Pinski <pinskia at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Assignee|pinskia at gcc dot gnu.org |unassigned at gcc dot gnu.org
Known to work| |12.1.0
Status|ASSIGNED |NEW
--- Comment #3 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Starting in GCC 12 we produce:
vect__1.5_10 = *a_4(D);
vect__2.6_11 = VEC_PERM_EXPR <vect__1.5_10, vect__1.5_10, { 1, 0 }>;
*b_6(D) = vect__2.6_11;
ldr q0, [x0]
ext v0.16b, v0.16b, v0.16b, #8
str q0, [x1]
RTL level wise:
Trying 8 -> 9:
8: r96:V2DI=unspec[r92:V2DI,r92:V2DI,0x1] 237
REG_DEAD r92:V2DI
9: [r98:DI]=r96:V2DI
REG_DEAD r98:DI
REG_DEAD r96:V2DI
Failed to match this instruction:
(set (mem:V2DI (reg:DI 98) [1 *b_6(D)+0 S16 A128])
(unspec:V2DI [
(reg:V2DI 92 [ vect__1.5 ]) repeated x2
(const_int 1 [0x1])
] UNSPEC_EXT))
Trying 7, 8 -> 9:
7: r92:V2DI=[r97:DI]
REG_DEAD r97:DI
8: r96:V2DI=unspec[r92:V2DI,r92:V2DI,0x1] 237
REG_DEAD r92:V2DI
9: [r98:DI]=r96:V2DI
REG_DEAD r98:DI
REG_DEAD r96:V2DI
Failed to match this instruction:
(set (mem:V2DI (reg:DI 98) [1 *b_6(D)+0 S16 A128])
(unspec:V2DI [
(mem:V2DI (reg:DI 97) [1 *a_4(D)+0 S16 A128]) repeated x2
(const_int 1 [0x1])
] UNSPEC_EXT))
Maybe the aarch64 backend could have a pattern that matches the last 7,8 -> 9
combined rtl that then expands into a load pair/store pair with reversed
registers.
^ permalink raw reply [flat|nested] 6+ messages in thread
* [Bug target/98532] Use load/store pairs for 2-element vector in memory permutes
2021-01-05 14:08 [Bug target/98532] New: Use load/store pairs for 2-element vector in memory permutes ktkachov at gcc dot gnu.org
` (3 preceding siblings ...)
2023-05-12 5:34 ` pinskia at gcc dot gnu.org
@ 2024-02-27 8:27 ` pinskia at gcc dot gnu.org
4 siblings, 0 replies; 6+ messages in thread
From: pinskia at gcc dot gnu.org @ 2024-02-27 8:27 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98532
Andrew Pinski <pinskia at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Resolution|--- |FIXED
Target Milestone|--- |12.0
Status|NEW |RESOLVED
--- Comment #4 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Fixed by enabling SLP at -O2. Though this could be improved without the SLP.
_1 = BIT_FIELD_REF <*a_4(D), 64, 64>;
_2 = BIT_FIELD_REF <*a_4(D), 64, 0>;
tmp_5 = {_1, _2};
Could be turned into VEC_PERM<*a_4(D), {1, 0}> earlier on. But I doubt that it
will matter so much really.
^ permalink raw reply [flat|nested] 6+ messages in thread
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2021-01-05 14:08 [Bug target/98532] New: Use load/store pairs for 2-element vector in memory permutes ktkachov at gcc dot gnu.org
2021-01-06 8:43 ` [Bug target/98532] " rguenth at gcc dot gnu.org
2021-02-08 2:32 ` pinskia at gcc dot gnu.org
2021-02-08 4:40 ` pinskia at gcc dot gnu.org
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