[Bug target/98867] New: Failure to use SRI instruction for shift-right-and-insert vector operations

[Bug target/98867] New: Failure to use SRI instruction for shift-right-and-insert vector operations

[ktkachov at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98867

            Bug ID: 98867
           Summary: Failure to use SRI instruction for
                    shift-right-and-insert vector operations
           Product: gcc
           Version: unknown
            Status: UNCONFIRMED
          Keywords: missed-optimization
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: ktkachov at gcc dot gnu.org
  Target Milestone: ---
            Target: aarch64

#define N 1024
unsigned char in[N];
unsigned char out[N];

#define SHIFT 6

void
foo (void)
{
  for (int i = 0; i < N; i++)
    {
      unsigned char mask = 255u >> SHIFT;
      unsigned char shifted = in[i] >> SHIFT;
      out[i] = (out[i] & ~mask) | shifted;
    }
}

at -O3 generates:
foo:
        adrp    x1, .LANCHOR0
        add     x1, x1, :lo12:.LANCHOR0
        movi    v2.16b, 0xfffffffffffffffc
        add     x2, x1, 1024
        mov     x0, 0
.L2:
        ldr     q0, [x1, x0]
        ldr     q1, [x0, x2]
        and     v0.16b, v0.16b, v2.16b
        ushr    v1.16b, v1.16b, 6
        orr     v0.16b, v0.16b, v1.16b
        str     q0, [x1, x0]
        add     x0, x0, 16
        cmp     x0, 1024
        bne     .L2
        ret

whereas it could use the SRI instruction as clang does (unrolled 2x):
foo:                                    // @foo
        adrp    x9, in
        adrp    x10, out
        mov     x8, xzr
        add     x9, x9, :lo12:in
        add     x10, x10, :lo12:out
.LBB0_1:                                // %vector.body
        add     x11, x9, x8
        add     x12, x10, x8
        ldp     q0, q1, [x11]
        ldp     q2, q3, [x12]
        add     x8, x8, #32                     // =32
        cmp     x8, #1024                       // =1024
        sri     v2.16b, v0.16b, #6
        sri     v3.16b, v1.16b, #6
        stp     q2, q3, [x12]
        b.ne    .LBB0_1

This may be a bit too complex for combine to match though

[Bug target/98867] Failure to use SRI instruction for shift-right-and-insert vector operations

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98867

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Last reconfirmed|                            |2021-02-04
           Severity|normal                      |enhancement
     Ever confirmed|0                           |1
             Status|UNCONFIRMED                 |NEW

--- Comment #1 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
>This may be a bit too complex for combine to match though
I don't think so really:

Trying 18, 13 -> 19:
   18: r110:V16QI=r111:V16QI&r112:V16QI
      REG_DEAD r111:V16QI
      REG_EQUAL r111:V16QI&const_vector
   13: r106:V16QI=r107:V16QI 0>>const_vector
      REG_DEAD r107:V16QI
   19: r113:V16QI=r106:V16QI|r110:V16QI
      REG_DEAD r110:V16QI
      REG_DEAD r106:V16QI
Failed to match this instruction:
(set (reg:V16QI 113 [ vect__6.15 ])
    (ior:V16QI (and:V16QI (reg:V16QI 111 [ MEM[symbol: out, index: ivtmp.22_30,
offset: 0B] ])
            (reg:V16QI 112))
        (lshiftrt:V16QI (reg:V16QI 107 [ MEM[symbol: in, index: ivtmp.22_30,
offset: 0B] ])
            (const_vector:V16QI [
                    (const_int 6 [0x6]) repeated x16
                ]))))


The only problem is (reg:V16QI 112) was not replaced with const_vector, that it
was formed from.
But insn 18 does have this REG_EQUAL:
        (expr_list:REG_EQUAL (and:V16QI (reg:V16QI 111 [ MEM[symbol: out,
index: ivtmp.22_30, offset: 0B] ])
                (const_vector:V16QI [
                        (const_int -4 [0xfffffffffffffffc]) repeated x16
                    ]))

So it might be easy to match, just combine is not showing all of what is being
tried?
So maybe adding a pattern for it might be easy ....