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From: "rguenth at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/99648] [11 regression] gcc.dg/torture/pr71522.c fails starting with r11-165 for 32 bits
Date: Wed, 31 Mar 2021 07:41:03 +0000	[thread overview]
Message-ID: <bug-99648-4-6rcBeZzdr0@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-99648-4@http.gcc.gnu.org/bugzilla/>

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99648

--- Comment #5 from Richard Biener <rguenth at gcc dot gnu.org> ---
(In reply to seurer from comment #4)
> Which RTL do you want to see?

So with a cross .expand shows we expand from

  MEM <unsigned long long> [(char * {ref-all})&d] = 4702111234474983680;
  MEM <unsigned char[8]> [(char * {ref-all})&s] = MEM <unsigned char[8]> [(char
* {ref-all})&d];
  _1 = __builtin_strcmp (&s, "AAAAAAA");
  if (_1 != 0)

doing

;; MEM <unsigned long long> [(char * {ref-all})&d] = 4702111234474983680;

(insn 5 4 6 (set (reg:SI 121)
        (high:SI (symbol_ref:SI ("*.LANCHOR0") [flags 0x182])))
"pr71522.c":20:3 -1
     (nil))

(insn 6 5 7 (set (reg/f:SI 120)
        (lo_sum:SI (reg:SI 121)
            (symbol_ref:SI ("*.LANCHOR0") [flags 0x182]))) "pr71522.c":20:3 -1
     (expr_list:REG_EQUAL (symbol_ref:SI ("*.LANCHOR0") [flags 0x182])
        (nil)))

(insn 7 6 0 (set (reg/v:DF 118 [ d ])
        (mem/u/c:DF (reg/f:SI 120) [0  S8 A64])) "pr71522.c":20:3 -1
     (expr_list:REG_EQUAL (const_double:DF 2.26163450980389118194580078125e+6
[0x0.8a0a0a0a0a08p+22])
        (nil)))

;; MEM <unsigned char[8]> [(char * {ref-all})&s] = MEM <unsigned char[8]>
[(char * {ref-all})&d];

(insn 8 7 0 (set (mem/c:DI (reg/f:SI 112 virtual-stack-vars) [0 MEM <unsigned
char[8]> [(char * {ref-all})&s]+0 S8 A64])
        (subreg:DI (reg/v:DF 118 [ d ]) 0)) "pr71522.c":21:3 -1
     (nil))


that looks OK, but then the assembly I get is

main:
.LFB0:
        stwu 1,-32(1)
.LCFI0:
        mflr 0
        stw 0,36(1)
.LCFI1:
        lis 9,.LANCHOR0@ha
        la 4,.LANCHOR0@l(9)
        lwz 10,0(4)
        lwz 11,4(4)
        stw 10,8(1)
        stw 11,12(1)
        addi 4,4,8
        addi 3,1,8
        bl strcmp

so no signs of 'lfd'.

How do you configure?  What subtarget do you use?  Problematic in the above
IL might be the reg-equal note.

  parent reply	other threads:[~2021-03-31  7:41 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-18 15:31 [Bug other/99648] New: " seurer at gcc dot gnu.org
2021-03-18 16:42 ` [Bug other/99648] " jakub at gcc dot gnu.org
2021-03-19  7:39 ` [Bug target/99648] " rguenth at gcc dot gnu.org
2021-03-30 20:01 ` seurer at gcc dot gnu.org
2021-03-30 20:06 ` seurer at gcc dot gnu.org
2021-03-31  7:41 ` rguenth at gcc dot gnu.org [this message]
2021-04-09 16:48 ` jakub at gcc dot gnu.org
2021-04-09 17:42 ` jakub at gcc dot gnu.org
2021-04-12  6:44 ` rguenth at gcc dot gnu.org
2021-04-12  9:10 ` jakub at gcc dot gnu.org
2021-04-12 10:27 ` jakub at gcc dot gnu.org
2021-04-12 11:30 ` rguenth at gcc dot gnu.org
2021-04-12 11:34 ` jakub at gcc dot gnu.org
2021-04-13  7:42 ` cvs-commit at gcc dot gnu.org
2021-04-13  7:42 ` jakub at gcc dot gnu.org

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