[Bug target/99766] New: ICE: unable to generate reloads with SVE code

[Bug target/99766] New: ICE: unable to generate reloads with SVE code

[ktkachov at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99766

            Bug ID: 99766
           Summary: ICE: unable to generate reloads with SVE code
           Product: gcc
           Version: 11.0
            Status: UNCONFIRMED
          Keywords: ice-on-valid-code
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: ktkachov at gcc dot gnu.org
  Target Milestone: ---
            Target: aarch64

#include <arm_sve.h>
#include <vector>
typedef float b __attribute__((__mode__(HF)));
typedef struct {
  b c;
  b d;
} e;
int f;
e *g;
void l(int s) {
  std::vector<e> m(s);
  for (; f;) {
    auto a = &g[0];
    for (int i;; ++i) {
      int n = i;
      auto o = &a[n];
      auto p = &m[i];
      float16_t q;
      for (int k; k < s;)
        for (int j; j < i; ++j) {
          auto r = o;
          for (k = 0; k < s; ++k)
            p[k].c = r[k].c * r[k].d;
        }
      for (int k; k < s; ++k) {
        p[k].c *= q;
        p[k].d *= q;
      }
    }
  }
}

With -std=c++17 -O3  -march=armv8.5-a+sve2 ICEs with:
ice.c: In function 'void l(int)':
ice.c:31:1: error: unable to generate reloads for:
   31 | }
      | ^
(insn 312 308 326 39 (set (subreg:VNx4SI (reg:VNx8HF 105 [ _17 ]) 0)
        (unspec:VNx4SI [
                (subreg:VNx4BI (reg:VNx16BI 365) 0)
                (vec_duplicate:VNx4SI (mem/c:SI (plus:DI (reg/f:DI 64 sfp)
                            (const_int 272 [0x110])) [12  S4 A128]))
                (const_vector:VNx4SI [
                        (const_int 0 [0])
                    ])
            ] UNSPEC_SEL)) 4825 {sve_ld1rvnx4si}
     (nil))
during RTL pass: reload

This seems to be very recent. A trunk from 23 March doesn't ICE

[Bug target/99766] [11 Regression] ICE: unable to generate reloads with SVE code

[ktkachov at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99766

ktkachov at gcc dot gnu.org changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Target Milestone|---                         |11.0
           Priority|P3                          |P1
      Known to work|                            |10.2.1
            Summary|ICE: unable to generate     |[11 Regression] ICE: unable
                   |reloads with SVE code       |to generate reloads with
                   |                            |SVE code
      Known to fail|                            |11.0

[Bug target/99766] [11 Regression] ICE: unable to generate reloads with SVE code

[acoplan at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99766

Alex Coplan <acoplan at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Last reconfirmed|                            |2021-03-25
     Ever confirmed|0                           |1
             Status|UNCONFIRMED                 |NEW
                 CC|                            |acoplan at gcc dot gnu.org

--- Comment #1 from Alex Coplan <acoplan at gcc dot gnu.org> ---
Confirmed. Here is a testcase without the includes:

typedef float a __attribute__((__mode__(HF)));
typedef struct {
  a b;
  a c;
} d;
int e;
d *f, *g;
__fp16 h;
void j() {
  for (int i;; ++i) {
    auto l = &f[i];
    for (int k; k < e;) {
      k = 0;
      for (; k < e; ++k)
        g[k].b = l[k].b * l[k].c;
    }
    for (int k; k < e; ++k) {
      g[k].b *= h;
      g[k].c *= h;
    }
  }
}

[Bug target/99766] [11 Regression] ICE: unable to generate reloads with SVE code

[acoplan at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99766

--- Comment #2 from Alex Coplan <acoplan at gcc dot gnu.org> ---
The above ICEs with just -O3 -march=armv8.2-a+sve.

[Bug target/99766] [11 Regression] ICE: unable to generate reloads with SVE code since r11-7807-gbe70bb5e

[acoplan at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99766

Alex Coplan <acoplan at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
            Summary|[11 Regression] ICE: unable |[11 Regression] ICE: unable
                   |to generate reloads with    |to generate reloads with
                   |SVE code                    |SVE code since
                   |                            |r11-7807-gbe70bb5e
                 CC|                            |vmakarov at gcc dot gnu.org

--- Comment #3 from Alex Coplan <acoplan at gcc dot gnu.org> ---
Started with r11-7807-gbe70bb5e4babdf9d3d33e8f4658452038407fa8e:

commit be70bb5e4babdf9d3d33e8f4658452038407fa8e
Author: Vladimir N. Makarov <vmakarov@redhat.com>
Date:   Tue Mar 23 17:51:21 2021 -0400

    [PR99581] Use relaxed memory for more aarch64 memory constraints

    The original patch for PR99581 resulted in GCC testsuite regression as
    some constraints were not declared as relaxed memory ones.  This patch
    fixes this.

[Bug target/99766] [11 Regression] ICE: unable to generate reloads with SVE code since r11-7807-gbe70bb5e

[vmakarov at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99766

--- Comment #4 from Vladimir Makarov <vmakarov at gcc dot gnu.org> ---
(In reply to Alex Coplan from comment #2)
> The above ICEs with just -O3 -march=armv8.2-a+sve.

Thank you for reporting.  I reproduced it тоо. I think соме constraint was not
categorized rightly.  It might be simply to find and to fix but it will need a
lot of testing.

[Bug target/99766] [11 Regression] ICE: unable to generate reloads with SVE code since r11-7807-gbe70bb5e

[rsandifo at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99766

rsandifo at gcc dot gnu.org <rsandifo at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |rsandifo at gcc dot gnu.org

--- Comment #5 from rsandifo at gcc dot gnu.org <rsandifo at gcc dot gnu.org> ---
I wonder if the CT_RELAXED_MEMORY cases should be following
on from CT_MEMORY rather than CT_SPECIAL_MEMORY.  They're really
normal memory constraints that just happen to accept more than
a standard constraint.

[Bug target/99766] [11 Regression] ICE: unable to generate reloads with SVE code since r11-7807-gbe70bb5e

[vmakarov at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99766

--- Comment #6 from Vladimir Makarov <vmakarov at gcc dot gnu.org> ---
(In reply to rsandifo@gcc.gnu.org from comment #5)
> I wonder if the CT_RELAXED_MEMORY cases should be following
> on from CT_MEMORY rather than CT_SPECIAL_MEMORY.  They're really
> normal memory constraints that just happen to accept more than
> a standard constraint.

Yes, this is the right question.  The patch I am working on treats
CT_SPECIAL_MEMORY the same way as CT_MEMORY everywhere although it is enough to
do this only in lra-constraints.c.

After finishing testing I'll commit the patch. Unfortunately compiler farm
arm64 machines are too slow (2 runs of gcc tests take almost 8 hours to run
with -j8).  I guess I'll fix it tomorrow.

[Bug target/99766] [11 Regression] ICE: unable to generate reloads with SVE code since r11-7807-gbe70bb5e

[acoplan at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99766

--- Comment #7 from Alex Coplan <acoplan at gcc dot gnu.org> ---
Here is a testcase with SVE intrinsics that ICEs in the same way at -Os:

$ cat test.cc
#include <arm_sve.h>
char a;
void c(unsigned &, const unsigned &);
void d(char, bool, short, int, int, char e, int, short f, unsigned g) {
  for (int h; h; h++)
    c(g, f);
  while (e)
    a = svaddv(svptrue_pat_b8(SV_VL1),
        svadd_z(svptrue_b8 (), svdup_s8(g), 0));
}
$ aarch64-linux-gnu-gcc -c -Os test.cc -march=armv8.2-a+sve
test.cc: In function ‘void d(char, bool, short int, int, int, char, int, short
int, unsigned int)’:
test.cc:10:1: error: unable to generate reloads for:
   10 | }
      | ^
(insn 39 89 40 5 (set (reg:VNx16QI 121 [ _5 ])
        (unspec:VNx16QI [
                (reg:VNx16BI 119)
                (vec_duplicate:VNx16QI (mem/c:QI (plus:DI (reg/f:DI 65 ap)
                            (const_int 64 [0x40])) [1 g+0 S1 A128]))
                (const_vector:VNx16QI [
                        (const_int 0 [0])
                    ])
            ] UNSPEC_SEL)) "test.cc":8:15 4782 {sve_ld1rvnx16qi}
     (expr_list:REG_DEAD (reg:VNx16BI 119)
        (nil)))
during RTL pass: reload
test.cc:10:1: internal compiler error: in curr_insn_transform, at
lra-constraints.c:4133

[Bug target/99766] [11 Regression] ICE: unable to generate reloads with SVE code since r11-7807-gbe70bb5e

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99766

--- Comment #8 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Vladimir Makarov <vmakarov@gcc.gnu.org>:

https://gcc.gnu.org/g:0d37e2d3ead072ba57e03fcb97a041504a22e721

commit r11-7864-g0d37e2d3ead072ba57e03fcb97a041504a22e721
Author: Vladimir Makarov <vmakarov@redhat.com>
Date:   Fri Mar 26 17:09:24 2021 +0000

    [PR99766] Consider relaxed memory associated more with memory instead of
special memory.

    Relaxed memory should be considered more like memory then special memory.

    gcc/ChangeLog:

            PR target/99766
            * ira-costs.c (record_reg_classes): Put case with
            CT_RELAXED_MEMORY adjacent to one with CT_MEMORY.
            * ira.c (ira_setup_alts): Ditto.
            * lra-constraints.c (process_alt_operands): Ditto.
            * recog.c (asm_operand_ok): Ditto.
            * reload.c (find_reloads): Ditto.

    gcc/testsuite/ChangeLog:

            PR target/99766
            * g++.target/aarch64/sve/pr99766.C: New.

[Bug target/99766] [11 Regression] ICE: unable to generate reloads with SVE code since r11-7807-gbe70bb5e

[vmakarov at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99766

Vladimir Makarov <vmakarov at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |marxin at gcc dot gnu.org

--- Comment #9 from Vladimir Makarov <vmakarov at gcc dot gnu.org> ---
*** Bug 99787 has been marked as a duplicate of this bug. ***

[Bug target/99766] [11 Regression] ICE: unable to generate reloads with SVE code since r11-7807-gbe70bb5e

[ktkachov at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99766

ktkachov at gcc dot gnu.org changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|NEW                         |RESOLVED
         Resolution|---                         |FIXED

--- Comment #10 from ktkachov at gcc dot gnu.org ---
Fixed, thanks.

[Bug target/99766] [11 Regression] ICE: unable to generate reloads with SVE code since r11-7807-gbe70bb5e

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99766

--- Comment #11 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The trunk branch has been updated by Andrew Pinski <pinskia@gcc.gnu.org>:

https://gcc.gnu.org/g:5fa4f982636e7e66eee6a9b45cc0939ae95b4659

commit r12-6164-g5fa4f982636e7e66eee6a9b45cc0939ae95b4659
Author: Andrew Pinski <apinski@marvell.com>
Date:   Sat Jan 1 08:44:48 2022 +0000

    Committed: Add testcases for a few PRs

    These were fixed as part of the fix for PR 99766,
    I thought it would be useful to add a few testcases
    for the other cases that were failing.

    Committed as obvious after running the tests to make
    sure they work.

            PR rtl-optimization/100241
            PR rtl-optimization/99787

    gcc/testsuite/ChangeLog:

            * gcc.c-torture/compile/pr100241-1.c: New test.
            * gcc.c-torture/compile/pr99787-1.c: New test.

[Bug target/99766] [11 Regression] ICE: unable to generate reloads with SVE code since r11-7807-gbe70bb5e

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99766

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |mpolacek at gcc dot gnu.org

--- Comment #12 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
*** Bug 100241 has been marked as a duplicate of this bug. ***