[Bug target/99842] New: MMA test case ICEs using -O3

[Bug target/99842] New: MMA test case ICEs using -O3

[bergner at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99842

            Bug ID: 99842
           Summary: MMA test case ICEs using -O3
           Product: gcc
           Version: 11.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: bergner at gcc dot gnu.org
  Target Milestone: ---

A reduced test case from Eigen using MMA builtins ICEs using -O3:

bergner@pike:~/gcc/BUGS/$ g++ -w -S -O3 -mcpu=power10 bug.ii 
bug.ii: In function ‘n< <template-parameter-1-1>, <anonymous>, m, <anonymous>,
<anonymous>, <anonymous> >::n(ab) [with ab = af<ag<int, const n<double, -1, -1,
3>, const n<double, -1, -1, 3> >, n<double, -1, 1, 3> >; cg = double; int
<anonymous> = -1; int m = 1; int <anonymous> = 3; int <anonymous> = 0; int
<anonymous> = 1]’:
bug.ii:90:59: error: could not split insn
   90 |   template <typename ab> n(ab p) { n::template ch<ab>(p); }
      |                                                           ^
(insn:TI 28 335 29 (set (reg:OO 32 0 [orig:125 _28 ] [125])
        (unspec:OO [
                (mem:V16QI (plus:DI (reg/f:DI 26 26 [orig:223 MEM <double *>
[(struct ca *)_253] ] [223])
                        (reg:DI 27 27 [222])) [0 MEM <au> [(void *)_25]+0 S16
A8])
                (mem:V16QI (plus:DI (reg/f:DI 26 26 [orig:223 MEM <double *>
[(struct ca *)_253] ] [223])
                        (reg:DI 27 27 [222])) [0 MEM <au> [(void *)_25]+0 S16
A8])
            ] UNSPEC_MMA_ASSEMBLE)) 2080 {*vsx_assemble_pair}
     (expr_list:REG_EQUIV (mem/c:OO (plus:DI (reg/f:DI 31 31 [217])
                (const_int 160 [0xa0])) [6 MEM[(__vector_pair *)_173]+0 S32
A256])
        (nil)))
during RTL pass: final
bug.ii:90:59: internal compiler error: in final_scan_insn_1, at final.c:3092
0x101fa5fb _fatal_insn(char const*, rtx_def const*, char const*, int, char
const*)
        /home/bergner/gcc/gcc-fsf-mainline-base/gcc/rtl-error.c:108
0x10a2b5cb final_scan_insn_1
        /home/bergner/gcc/gcc-fsf-mainline-base/gcc/final.c:3092
0x10a2c613 final_scan_insn(rtx_insn*, _IO_FILE*, int, int, int*)
        /home/bergner/gcc/gcc-fsf-mainline-base/gcc/final.c:3171
0x10a2c9b3 final_1
        /home/bergner/gcc/gcc-fsf-mainline-base/gcc/final.c:2022
0x10a2dc57 rest_of_handle_final
        /home/bergner/gcc/gcc-fsf-mainline-base/gcc/final.c:4676
0x10a2dc57 execute
        /home/bergner/gcc/gcc-fsf-mainline-base/gcc/final.c:4754

[Bug target/99842] MMA test case ICEs using -O3

[bergner at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99842

Peter Bergner <bergner at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Target|                            |powerpc64le-linux
     Ever confirmed|0                           |1
      Known to fail|                            |11.0
           Assignee|unassigned at gcc dot gnu.org      |bergner at gcc dot gnu.org
   Last reconfirmed|                            |2021-03-30
             Status|UNCONFIRMED                 |ASSIGNED
   Target Milestone|---                         |11.0

--- Comment #1 from Peter Bergner <bergner at gcc dot gnu.org> ---
Mine.  The problem is that the mma_assemble_input_operand predicate is
rejecting valid reg+reg indexed addresses in the MEMs in the above rtl.  The
predicate is calling quad_address_p() which accepts reg+offset addresses (with
constrained offset values), but doesn't allow reg+reg addresses, which are
valid.

Replacing the MEM_P() && quad_address_p() test with a call to memory_operand()
fixes the ICE, since it calls down to rs6000_legitimate_address_p(), which
calls quad_address_p() to validate reg+offset addresses, but also allows
reg+reg addresses.  I'll submit a patch with that fix.

[Bug target/99842] MMA test case ICEs using -O3

[jakub at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99842

Jakub Jelinek <jakub at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Target Milestone|11.0                        |11.2

--- Comment #2 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
GCC 11.1 has been released, retargeting bugs to GCC 11.2.

[Bug target/99842] MMA test case ICEs using -O3

[bergner at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99842

Peter Bergner <bergner at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
      Known to fail|                            |12.0
                URL|https://gcc.gnu.org/piperma |https://gcc.gnu.org/piperma
                   |il/gcc-patches/2021-March/5 |il/gcc-patches/2021-May/571
                   |67496.html                  |012.html

--- Comment #3 from Peter Bergner <bergner at gcc dot gnu.org> ---
Updated patch submitted.

[Bug target/99842] MMA test case ICEs using -O3

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99842

--- Comment #4 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Peter Bergner <bergner@gcc.gnu.org>:

https://gcc.gnu.org/g:df4e0359dad239854af0ea9eacb8e7e3719557d0

commit r12-1127-gdf4e0359dad239854af0ea9eacb8e7e3719557d0
Author: Peter Bergner <bergner@linux.ibm.com>
Date:   Sun May 30 22:45:55 2021 -0500

    rs6000: MMA test case ICEs using -O3 [PR99842]

    The mma_assemble_input_operand predicate does not accept reg+reg indexed
    addresses which can lead to ICEs.  The lxv and lxvp instructions have
    indexed forms (lxvx and lxvpx), so the simple solution is to just allow
    indexed addresses in the predicate.

    2021-05-30  Peter Bergner  <bergner@linux.ibm.com>

    gcc/
            PR target/99842
            * config/rs6000/predicates.md(mma_assemble_input_operand): Allow
            indexed form addresses.

    gcc/testsuite/
            PR target/99842
            * g++.target/powerpc/pr99842.C: New.

[Bug target/99842] MMA test case ICEs using -O3

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99842

--- Comment #5 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-11 branch has been updated by Peter Bergner
<bergner@gcc.gnu.org>:

https://gcc.gnu.org/g:aaa8419bcf2ec491c0fd41a526f5817da0cf3ed4

commit r11-8608-gaaa8419bcf2ec491c0fd41a526f5817da0cf3ed4
Author: Peter Bergner <bergner@linux.ibm.com>
Date:   Sun May 30 22:45:55 2021 -0500

    rs6000: MMA test case ICEs using -O3 [PR99842]

    The mma_assemble_input_operand predicate does not accept reg+reg indexed
    addresses which can lead to ICEs.  The lxv and lxvp instructions have
    indexed forms (lxvx and lxvpx), so the simple solution is to just allow
    indexed addresses in the predicate.

    2021-05-30  Peter Bergner  <bergner@linux.ibm.com>

    gcc/
            PR target/99842
            * config/rs6000/predicates.md(mma_assemble_input_operand): Allow
            indexed form addresses.

    gcc/testsuite/
            PR target/99842
            * g++.target/powerpc/pr99842.C: New.

    (cherry picked from commit df4e0359dad239854af0ea9eacb8e7e3719557d0)

[Bug target/99842] MMA test case ICEs using -O3

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99842

--- Comment #6 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-10 branch has been updated by Peter Bergner
<bergner@gcc.gnu.org>:

https://gcc.gnu.org/g:206d49a23735168769065716c4b211328dbf1b76

commit r10-9929-g206d49a23735168769065716c4b211328dbf1b76
Author: Peter Bergner <bergner@linux.ibm.com>
Date:   Sun May 30 22:45:55 2021 -0500

    rs6000: MMA test case ICEs using -O3 [PR99842]

    The mma_assemble_input_operand predicate does not accept reg+reg indexed
    addresses which can lead to ICEs.  The lxv and lxvp instructions have
    indexed forms (lxvx and lxvpx), so the simple solution is to just allow
    indexed addresses in the predicate.

    2021-05-30  Peter Bergner  <bergner@linux.ibm.com>

    gcc/
            PR target/99842
            * config/rs6000/predicates.md(mma_assemble_input_operand): Allow
            indexed form addresses.

    gcc/testsuite/
            PR target/99842
            * g++.target/powerpc/pr99842.C: New.

    (cherry picked from commit df4e0359dad239854af0ea9eacb8e7e3719557d0)

[Bug target/99842] MMA test case ICEs using -O3

[bergner at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99842

Peter Bergner <bergner at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
         Resolution|---                         |FIXED
             Status|ASSIGNED                    |RESOLVED

--- Comment #7 from Peter Bergner <bergner at gcc dot gnu.org> ---
Fixed everywhere.