[Bug c++/99908] New: Arm optimisation generates a `not` instruction instead of switching arguments of bsl

[Bug c++/99908] New: Arm optimisation generates a `not` instruction instead of switching arguments of bsl

[denis.yaroshevskij at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99908

            Bug ID: 99908
           Summary: Arm optimisation generates a `not` instruction instead
                    of switching arguments of bsl
           Product: gcc
           Version: unknown
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: c++
          Assignee: unassigned at gcc dot gnu.org
          Reporter: denis.yaroshevskij at gmail dot com
  Target Milestone: ---

Similar to https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98461

Suboptimal codegen for simd negation of a logical + if_else
https://godbolt.org/z/WPE3cx75z

[Bug target/99908] SIMD: negating logical + if_else has a suboptimal codegen.

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99908

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Severity|normal                      |enhancement
           Keywords|                            |missed-optimization

[Bug target/99908] SIMD: negating logical + if_else has a suboptimal codegen.

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99908

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |NEW
   Last reconfirmed|                            |2021-04-06
     Ever confirmed|0                           |1
            Version|unknown                     |11.0

--- Comment #1 from Richard Biener <rguenth at gcc dot gnu.org> ---
Confirmed.  On GIMPLE the intrinsics are opaque:

  <bb 2> [local count: 1073741824]:
  _10 = __builtin_ia32_andnotsi256 (mask_3(D), { -1, -1, -1, -1 });
  _7 = VIEW_CONVERT_EXPR<vector(32) char>(_10);
  _4 = VIEW_CONVERT_EXPR<vector(32) char>(b_6(D));
  _2 = VIEW_CONVERT_EXPR<vector(32) char>(a_5(D));
  _8 = __builtin_ia32_pblendvb256 (_2, _4, _7);
  _9 = VIEW_CONVERT_EXPR<__m256i>(_8);
  return _9;

and on RTL the blend is an UNSPEC:

(insn 14 13 15 2 (set (reg:V32QI 93)
        (unspec:V32QI [
                (reg:V32QI 94)
                (reg:V32QI 95)
                (reg:V32QI 96)
            ] UNSPEC_BLENDV)) "include/avx2intrin.h":209:20 -1
     (nil))

that makes it a target missed optimization.

[Bug target/99908] SIMD: negating logical + if_else has a suboptimal codegen.

[crazylht at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99908

--- Comment #2 from Hongtao.liu <crazylht at gmail dot com> ---
I'm testing

@@ -17759,6 +17759,35 @@ (define_insn "<sse4_1_avx2>_pblendvb"
    (set_attr "btver2_decode" "vector,vector,vector")
    (set_attr "mode" "<sseinsnmode>")])

+(define_split
+  [(set (match_operand:VI1_AVX2 0 "register_operand")
+       (unspec:VI1_AVX2
+         [(match_operand:VI1_AVX2 1 "vector_operand")
+          (match_operand:VI1_AVX2 2 "register_operand")
+          (not:VI1_AVX2 (match_operand:VI1_AVX2 3 "register_operand"))]
+         UNSPEC_BLENDV))]
+  "TARGET_SSE4_1"
+  [(set (match_dup 0)
+       (unspec:VI1_AVX2
+         [(match_dup 2) (match_dup 1) (match_dup 3)]
+         UNSPEC_BLENDV))])
+
+(define_split
+  [(set (match_operand:VI1_AVX2 0 "register_operand")
+       (unspec:VI1_AVX2
+         [(match_operand:VI1_AVX2 1 "vector_operand")
+          (match_operand:VI1_AVX2 2 "register_operand")
+          (subreg:VI1_AVX2 (not (match_operand 3 "register_operand")) 0)]
+         UNSPEC_BLENDV))]
+  "TARGET_SSE4_1
+   && GET_MODE_CLASS (GET_MODE (operands[3])) == MODE_VECTOR_INT
+   && GET_MODE_SIZE (GET_MODE (operands[3])) == <MODE_SIZE>"
+  [(set (match_dup 0)
+       (unspec:VI1_AVX2
+         [(match_dup 2) (match_dup 1) (match_dup 4)]
+         UNSPEC_BLENDV))]
+  "operands[4] = gen_lowpart (<MODE>mode, operands[3]);")
+

[Bug target/99908] SIMD: negating logical + if_else has a suboptimal codegen.

[crazylht at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99908

--- Comment #3 from Hongtao.liu <crazylht at gmail dot com> ---
Created attachment 50517
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=50517&action=edit
tested patch waiting for GCC12.

[Bug target/99908] SIMD: negating logical + if_else has a suboptimal codegen.

[crazylht at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99908

--- Comment #4 from Hongtao.liu <crazylht at gmail dot com> ---
A patch is posted at
https://gcc.gnu.org/pipermail/gcc-patches/2021-April/568785.html

[Bug target/99908] SIMD: negating logical + if_else has a suboptimal codegen.

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99908

--- Comment #5 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by hongtao Liu <liuhongt@gcc.gnu.org>:

https://gcc.gnu.org/g:8da3b309d8fb3ddec0b42218ca6762967b402dc3

commit r12-746-g8da3b309d8fb3ddec0b42218ca6762967b402dc3
Author: liuhongt <hongtao.liu@intel.com>
Date:   Wed Apr 7 09:58:54 2021 +0800

    i386: Optimize vpblendvb on inverted mask register to vpblendvb on swapping
the order of operand 1 and operand 2. [PR target/99908]

    -       vpcmpeqd        %ymm3, %ymm3, %ymm3
    -       vpandn  %ymm3, %ymm2, %ymm2
    -       vpblendvb       %ymm2, %ymm1, %ymm0, %ymm0
    +       vpblendvb       %ymm2, %ymm0, %ymm1, %ymm0

    gcc/ChangeLog:

            PR target/99908
            * config/i386/sse.md (<sse4_1_avx2>_pblendvb): Add
            splitters for pblendvb of NOT mask register.

    gcc/testsuite/ChangeLog:

            PR target/99908
            * gcc.target/i386/avx2-pr99908.c: New test.
            * gcc.target/i386/sse4_1-pr99908.c: New test.

[Bug target/99908] SIMD: negating logical + if_else has a suboptimal codegen.

[crazylht at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99908

--- Comment #6 from Hongtao.liu <crazylht at gmail dot com> ---
Should be fixed in trunk.

[Bug target/99908] SIMD: negating logical + if_else has a suboptimal codegen.

[rearnsha at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99908

--- Comment #7 from Richard Earnshaw <rearnsha at gcc dot gnu.org> ---
(In reply to Hongtao.liu from comment #6)
> Should be fixed in trunk.

The original report was about arm.  None of your changes are outside of the x86
backend, so no, this is not fixed for the original reporter.

[Bug target/99908] SIMD: negating logical + if_else has a suboptimal codegen.

[rearnsha at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99908

--- Comment #8 from Richard Earnshaw <rearnsha at gcc dot gnu.org> ---
Never mind, the original reference to arm was not the 'arm cpu', my mistake.

[Bug target/99908] SIMD: negating logical + if_else has a suboptimal codegen.

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99908

--- Comment #9 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Created attachment 55704
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=55704&action=edit
testcase

[Bug target/99908] SIMD: negating logical + if_else has a suboptimal codegen.

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99908

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
         Resolution|---                         |FIXED
             Status|NEW                         |RESOLVED
   Target Milestone|---                         |12.0

--- Comment #10 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Fixed.