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* [gcc(refs/users/meissner/heads/work055)] Revert patch.
@ 2021-06-11 22:17 Michael Meissner
0 siblings, 0 replies; 15+ messages in thread
From: Michael Meissner @ 2021-06-11 22:17 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:909af0b6f1e7bc68bffb76d45dce29656e0c6adb
commit 909af0b6f1e7bc68bffb76d45dce29656e0c6adb
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Jun 11 18:17:03 2021 -0400
Revert patch.
gcc/
2021-06-10 Michael Meissner <meissner@linux.ibm.com>
Revert patch.
PR target/101019
* config/rs6000/rs6000-cpus.def (ISA_3_1_MASKS_SERVER): Add
-mpower10-large-consts support.
(POWERPC_MASKS): Add -mpower10-large-consts support.
* config/rs6000/rs6000.c (rs6000_option_override_internal): Add
-mpower10-large-consts support.
(num_insns_constant_gpr): Add -mpower10-large-consts support.
(rs6000_emit_set_long_const): Add -mpower10-large-consts support.
(rs6000_opt_masks): Add -mpower10-large-consts.
* config/rs6000/rs6000.opt (-mpower10-large-consts): New switch.
gcc/testsuite/
2021-06-09 Michael Meissner <meissner@linux.ibm.com>
Revert patch.
PR target/101019
* gcc.target/powerpc/prefix-large-const.c: New test.
Diff:
---
gcc/config/rs6000/rs6000-cpus.def | 2 -
gcc/config/rs6000/rs6000.c | 50 ++--------------------
gcc/config/rs6000/rs6000.opt | 4 --
.../gcc.target/powerpc/prefix-large-const.c | 32 --------------
4 files changed, 4 insertions(+), 84 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def
index b119f574e4c..c0d89434fcd 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -90,7 +90,6 @@
| OPTION_MASK_P10_FUSION_LOGADD \
| OPTION_MASK_P10_FUSION_ADDLOG \
| OPTION_MASK_P10_FUSION_2ADD \
- | OPTION_MASK_P10_LARGE_CONSTS \
| OPTION_MASK_XXSPLTI32DX \
| OPTION_MASK_XXSPLTIDP \
| OPTION_MASK_XXSPLTIW)
@@ -146,7 +145,6 @@
| OPTION_MASK_P10_FUSION_LOGADD \
| OPTION_MASK_P10_FUSION_ADDLOG \
| OPTION_MASK_P10_FUSION_2ADD \
- | OPTION_MASK_P10_LARGE_CONSTS \
| OPTION_MASK_HTM \
| OPTION_MASK_ISEL \
| OPTION_MASK_LXVKQ \
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 93e14570ed3..ca92ee63d73 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -4489,12 +4489,6 @@ rs6000_option_override_internal (bool global_init_p)
&& (rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION_2ADD) == 0)
rs6000_isa_flags |= OPTION_MASK_P10_FUSION_2ADD;
- if (TARGET_PREFIXED
- && (rs6000_isa_flags_explicit & OPTION_MASK_P10_LARGE_CONSTS) == 0)
- rs6000_isa_flags |= OPTION_MASK_P10_LARGE_CONSTS;
- else if (!TARGET_PREFIXED)
- rs6000_isa_flags &= ~OPTION_MASK_P10_LARGE_CONSTS;
-
/* Turn off vector pair/mma options on non-power10 systems. */
else if (!TARGET_POWER10 && TARGET_MMA)
{
@@ -5965,20 +5959,9 @@ num_insns_constant_gpr (HOST_WIDE_INT value)
&& (value >> 31 == -1 || value >> 31 == 0))
return 1;
- /* PADDI can support up to 34 bit signed integers, or using a combination of
- PADDI and shift left. */
- else if (TARGET_P10_LARGE_CONSTS)
- {
- if (SIGNED_INTEGER_34BIT_P (value))
- return 1;
-
- /* PLI and SLDI. */
- if ((value & 0xffffffff) == 0)
- return 2;
-
- /* PLI, SLDI, PADDI. */
- return 3;
- }
+ /* PADDI can support up to 34 bit signed integers. */
+ else if (TARGET_PREFIXED && SIGNED_INTEGER_34BIT_P (value))
+ return 1;
else if (TARGET_POWERPC64)
{
@@ -10432,31 +10415,7 @@ rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c)
rtx two = gen_rtx_ASHIFT (DImode, temp, GEN_INT (32));
emit_move_insn (dest, gen_rtx_IOR (DImode, one, two));
}
- /* We can't load R0 using PLI/SLDA/PADDI, since the R0 in the PADDI would be
- interpreted as 0 and not register 0. */
- else if (TARGET_P10_LARGE_CONSTS
- && (base_reg_operand (dest, DImode)
- || can_create_pseudo_p ()
- || (ud1 == 0 && ud2 == 0)))
- {
- HOST_WIDE_INT low_32bit = ud1 | (ud2 << 16);
- HOST_WIDE_INT high_32bit = ud3 | (ud4 << 16);
-
- temp = !can_create_pseudo_p () ? copy_rtx (dest) : gen_reg_rtx (DImode);
- emit_move_insn (temp, GEN_INT (high_32bit));
-
- if (!low_32bit)
- emit_insn (gen_ashldi3 (dest, temp, GEN_INT (32)));
- else
- {
- rtx temp2 = (!can_create_pseudo_p ()
- ? copy_rtx (dest)
- : gen_reg_rtx (DImode));
- emit_insn (gen_ashldi3 (temp2, temp, GEN_INT (32)));
- emit_insn (gen_adddi3 (dest, temp2, GEN_INT (low_32bit)));
- }
- }
- else if ((ud4 == 0xaffff && (ud3 & 0x8000))
+ else if ((ud4 == 0xffff && (ud3 & 0x8000))
|| (ud4 == 0 && ! (ud3 & 0x8000)))
{
temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
@@ -24465,7 +24424,6 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
{ "power9-misc", OPTION_MASK_P9_MISC, false, true },
{ "power9-vector", OPTION_MASK_P9_VECTOR, false, true },
{ "power10-fusion", OPTION_MASK_P10_FUSION, false, true },
- { "power10-large-consts", OPTION_MASK_P10_LARGE_CONSTS, false, true },
{ "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT, false, true },
{ "powerpc-gpopt", OPTION_MASK_PPC_GPOPT, false, true },
{ "prefixed", OPTION_MASK_PREFIXED, false, true },
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index add22c8be1a..e65dd8762a4 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -655,7 +655,3 @@ Generate (do not generate) XXSPLTI32DX instructions.
mlxvkq
Target Undocumented Mask(LXVKQ) Var(rs6000_isa_flags)
Generate (do not generate) LXVKQ instructions.
-
-mpower10-large-consts
-Target Undocumented Mask(P10_LARGE_CONSTS) Var(rs6000_isa_flags)
-Generate (do not generate) PLI/SLDI/PADDI to load large constants.
diff --git a/gcc/testsuite/gcc.target/powerpc/prefix-large-const.c b/gcc/testsuite/gcc.target/powerpc/prefix-large-const.c
deleted file mode 100644
index fa4904efbc7..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/prefix-large-const.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target powerpc_prefixed_addr } */
-/* { dg-require-effective-target lp64 } */
-/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
-
-/* Test whether we can use PLI/PADDI to load up large constants. */
-
-long
-foo_1 (void)
-{
- return 1L << 53; /* LIS, SLDI. */
-}
-
-long
-foo_2 (void)
-{
- return (1L << 53) | (1L << 35); /* PLI, SLDI. */
-}
-
-long
-foo_3 (void)
-{
- return ((1L << 53) /* PLI, SLDI, PADDI. */
- | (1L << 35)
- | (1L << 30)
- | (1L << 2));
-}
-
-/* { dg-final { scan-assembler-times {\mlis\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mpaddi\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mpli\M} 2 } } */
-/* { dg-final { scan-assembler-times {\msldi\M} 3 } } */
^ permalink raw reply [flat|nested] 15+ messages in thread
* [gcc(refs/users/meissner/heads/work055)] Revert patch.
@ 2021-06-11 22:58 Michael Meissner
0 siblings, 0 replies; 15+ messages in thread
From: Michael Meissner @ 2021-06-11 22:58 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:256e55172ee7b94e1b861cd0c2cb65ceccb50e4b
commit 256e55172ee7b94e1b861cd0c2cb65ceccb50e4b
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Jun 11 18:58:15 2021 -0400
Revert patch.
gcc/
2021-06-11 Michael Meissner <meissner@linux.ibm.com>
Revert patch.
PR target/101019
* config/rs6000/rs6000-cpus.def (ISA_3_1_MASKS_SERVER): Add
-mpower10-large-consts support.
(POWERPC_MASKS): Add -mpower10-large-consts support.
* config/rs6000/rs6000.c (rs6000_option_override_internal): Add
-mpower10-large-consts support.
(num_insns_constant_gpr): Add -mpower10-large-consts support.
(rs6000_emit_set_long_const): Add -mpower10-large-consts support.
(rs6000_opt_masks): Add -mpower10-large-consts.
* config/rs6000/rs6000.opt (-mpower10-large-consts): New switch.
gcc/testsuite/
2021-06-11 Michael Meissner <meissner@linux.ibm.com>
Revert patch.
PR target/101019
* gcc.target/powerpc/prefix-large-const.c: New test.
Diff:
---
gcc/config/rs6000/rs6000-cpus.def | 2 -
gcc/config/rs6000/rs6000.c | 67 ++--------------------
gcc/config/rs6000/rs6000.opt | 4 --
.../gcc.target/powerpc/prefix-large-const.c | 50 ----------------
4 files changed, 4 insertions(+), 119 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def
index b119f574e4c..c0d89434fcd 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -90,7 +90,6 @@
| OPTION_MASK_P10_FUSION_LOGADD \
| OPTION_MASK_P10_FUSION_ADDLOG \
| OPTION_MASK_P10_FUSION_2ADD \
- | OPTION_MASK_P10_LARGE_CONSTS \
| OPTION_MASK_XXSPLTI32DX \
| OPTION_MASK_XXSPLTIDP \
| OPTION_MASK_XXSPLTIW)
@@ -146,7 +145,6 @@
| OPTION_MASK_P10_FUSION_LOGADD \
| OPTION_MASK_P10_FUSION_ADDLOG \
| OPTION_MASK_P10_FUSION_2ADD \
- | OPTION_MASK_P10_LARGE_CONSTS \
| OPTION_MASK_HTM \
| OPTION_MASK_ISEL \
| OPTION_MASK_LXVKQ \
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index ac01b46e864..ca92ee63d73 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -4489,12 +4489,6 @@ rs6000_option_override_internal (bool global_init_p)
&& (rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION_2ADD) == 0)
rs6000_isa_flags |= OPTION_MASK_P10_FUSION_2ADD;
- if (TARGET_PREFIXED
- && (rs6000_isa_flags_explicit & OPTION_MASK_P10_LARGE_CONSTS) == 0)
- rs6000_isa_flags |= OPTION_MASK_P10_LARGE_CONSTS;
- else if (!TARGET_PREFIXED)
- rs6000_isa_flags &= ~OPTION_MASK_P10_LARGE_CONSTS;
-
/* Turn off vector pair/mma options on non-power10 systems. */
else if (!TARGET_POWER10 && TARGET_MMA)
{
@@ -5965,20 +5959,9 @@ num_insns_constant_gpr (HOST_WIDE_INT value)
&& (value >> 31 == -1 || value >> 31 == 0))
return 1;
- /* PADDI can support up to 34 bit signed integers, or using a combination of
- PADDI and shift left. */
- else if (TARGET_P10_LARGE_CONSTS)
- {
- if (SIGNED_INTEGER_34BIT_P (value))
- return 1;
-
- /* PLI and SLDI. */
- if ((value & 0xffffffff) == 0)
- return 2;
-
- /* PLI, SLDI, PADDI. */
- return 3;
- }
+ /* PADDI can support up to 34 bit signed integers. */
+ else if (TARGET_PREFIXED && SIGNED_INTEGER_34BIT_P (value))
+ return 1;
else if (TARGET_POWERPC64)
{
@@ -10432,48 +10415,7 @@ rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c)
rtx two = gen_rtx_ASHIFT (DImode, temp, GEN_INT (32));
emit_move_insn (dest, gen_rtx_IOR (DImode, one, two));
}
- else if (TARGET_P10_LARGE_CONSTS)
- {
- HOST_WIDE_INT low_32bit = ud1 | (ud2 << 16);
- HOST_WIDE_INT high_32bit = ud3 | (ud4 << 16);
-
- temp = !can_create_pseudo_p () ? copy_rtx (dest) : gen_reg_rtx (DImode);
- emit_move_insn (temp, GEN_INT (high_32bit));
-
- if (!low_32bit)
- emit_insn (gen_ashldi3 (dest, temp, GEN_INT (32)));
- else
- {
- rtx temp2 = (!can_create_pseudo_p ()
- ? copy_rtx (dest)
- : gen_reg_rtx (DImode));
-
- emit_insn (gen_ashldi3 (temp2, temp, GEN_INT (32)));
-
- /* See if a simple ORI or ORIS will suffice to fill in the
- constant. */
- if (ud2 == 0)
- emit_insn (gen_iordi3 (dest, temp2, GEN_INT (ud1)));
- else if (ud1 == 0)
- emit_insn (gen_iordi3 (dest, temp2, GEN_INT (ud2 << 16)));
- /* If the register is not r0, we can do a PADDI. However, if the
- register is r0, we need to do an ORI and ORIS instead of a PADDI.
- This is because R0 as the register is interpreted as 0 and not
- R0. */
- else if (REGNO (dest) != FIRST_GPR_REGNO)
- emit_insn (gen_adddi3 (dest, temp2, GEN_INT (low_32bit)));
- else
- {
- rtx temp3 = (!can_create_pseudo_p ()
- ? copy_rtx (dest)
- : gen_reg_rtx (DImode));
-
- emit_insn (gen_iordi3 (temp3, temp2, GEN_INT (ud2 << 16)));
- emit_insn (gen_iordi3 (dest, temp3, GEN_INT (ud1)));
- }
- }
- }
- else if ((ud4 == 0xaffff && (ud3 & 0x8000))
+ else if ((ud4 == 0xffff && (ud3 & 0x8000))
|| (ud4 == 0 && ! (ud3 & 0x8000)))
{
temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
@@ -24482,7 +24424,6 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
{ "power9-misc", OPTION_MASK_P9_MISC, false, true },
{ "power9-vector", OPTION_MASK_P9_VECTOR, false, true },
{ "power10-fusion", OPTION_MASK_P10_FUSION, false, true },
- { "power10-large-consts", OPTION_MASK_P10_LARGE_CONSTS, false, true },
{ "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT, false, true },
{ "powerpc-gpopt", OPTION_MASK_PPC_GPOPT, false, true },
{ "prefixed", OPTION_MASK_PREFIXED, false, true },
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index add22c8be1a..e65dd8762a4 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -655,7 +655,3 @@ Generate (do not generate) XXSPLTI32DX instructions.
mlxvkq
Target Undocumented Mask(LXVKQ) Var(rs6000_isa_flags)
Generate (do not generate) LXVKQ instructions.
-
-mpower10-large-consts
-Target Undocumented Mask(P10_LARGE_CONSTS) Var(rs6000_isa_flags)
-Generate (do not generate) PLI/SLDI/PADDI to load large constants.
diff --git a/gcc/testsuite/gcc.target/powerpc/prefix-large-const.c b/gcc/testsuite/gcc.target/powerpc/prefix-large-const.c
deleted file mode 100644
index 50921326d5c..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/prefix-large-const.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target powerpc_prefixed_addr } */
-/* { dg-require-effective-target lp64 } */
-/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
-
-/* Test whether we can use PLI/PADDI to load up large constants. */
-
-long
-foo_1 (void)
-{
- return 1L << 53; /* LIS, SLDI. */
-}
-
-long
-foo_2 (void)
-{
- return (1L << 53) | (1L << 35); /* PLI, SLDI. */
-}
-
-long
-foo_3 (void)
-{
- return ((1L << 53) /* PLI, SLDI, PADDI. */
- | (1L << 35)
- | (1L << 30)
- | (1L << 2));
-}
-
-long
-foo_4 (void)
-{
- return ((1L << 53) /* PLI, SLDI, ORI. */
- | (1L << 35)
- | (1L << 2));
-}
-
-long
-foo_5 (void)
-{
- return ((1L << 53) /* PLI, SLDI, ORIS. */
- | (1L << 35)
- | (1L << 30));
-}
-
-/* { dg-final { scan-assembler-times {\mlis\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mori\M} 1 } } */
-/* { dg-final { scan-assembler-times {\moris\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mpaddi\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mpli\M} 4 } } */
-/* { dg-final { scan-assembler-times {\msldi\M} 5 } } */
^ permalink raw reply [flat|nested] 15+ messages in thread
* [gcc(refs/users/meissner/heads/work055)] Revert patch.
@ 2021-06-10 22:51 Michael Meissner
0 siblings, 0 replies; 15+ messages in thread
From: Michael Meissner @ 2021-06-10 22:51 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:d69367f2d3ffa90be72a1b52ad81692f0f25a33c
commit d69367f2d3ffa90be72a1b52ad81692f0f25a33c
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Jun 10 18:51:12 2021 -0400
Revert patch.
gcc/
2021-06-10 Michael Meissner <meissner@linux.ibm.com>
Revert patch.
PR target/101019
* config/rs6000/rs6000-cpus.def (ISA_3_1_MASKS_SERVER): Add
-mpower10-large-consts support.
(POWERPC_MASKS): Add -mpower10-large-consts support.
* config/rs6000/rs6000.c (rs6000_option_override_internal): Add
-mpower10-large-consts support.
(num_insns_constant_gpr): Add -mpower10-large-consts support.
(rs6000_emit_set_long_const): Add -mpower10-large-consts support.
(rs6000_opt_masks): Add -mpower10-large-consts.
* config/rs6000/rs6000.opt (-mpower10-large-consts): New switch.
gcc/testsuite/
2021-06-09 Michael Meissner <meissner@linux.ibm.com>
Revert patch.
PR target/101019
* gcc.target/powerpc/prefix-large-const.c: New test.
Diff:
---
gcc/config/rs6000/rs6000-cpus.def | 2 -
gcc/config/rs6000/rs6000.c | 50 ++--------------------
gcc/config/rs6000/rs6000.opt | 4 --
.../gcc.target/powerpc/prefix-large-const.c | 32 --------------
4 files changed, 4 insertions(+), 84 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def
index b119f574e4c..c0d89434fcd 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -90,7 +90,6 @@
| OPTION_MASK_P10_FUSION_LOGADD \
| OPTION_MASK_P10_FUSION_ADDLOG \
| OPTION_MASK_P10_FUSION_2ADD \
- | OPTION_MASK_P10_LARGE_CONSTS \
| OPTION_MASK_XXSPLTI32DX \
| OPTION_MASK_XXSPLTIDP \
| OPTION_MASK_XXSPLTIW)
@@ -146,7 +145,6 @@
| OPTION_MASK_P10_FUSION_LOGADD \
| OPTION_MASK_P10_FUSION_ADDLOG \
| OPTION_MASK_P10_FUSION_2ADD \
- | OPTION_MASK_P10_LARGE_CONSTS \
| OPTION_MASK_HTM \
| OPTION_MASK_ISEL \
| OPTION_MASK_LXVKQ \
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 93e14570ed3..ca92ee63d73 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -4489,12 +4489,6 @@ rs6000_option_override_internal (bool global_init_p)
&& (rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION_2ADD) == 0)
rs6000_isa_flags |= OPTION_MASK_P10_FUSION_2ADD;
- if (TARGET_PREFIXED
- && (rs6000_isa_flags_explicit & OPTION_MASK_P10_LARGE_CONSTS) == 0)
- rs6000_isa_flags |= OPTION_MASK_P10_LARGE_CONSTS;
- else if (!TARGET_PREFIXED)
- rs6000_isa_flags &= ~OPTION_MASK_P10_LARGE_CONSTS;
-
/* Turn off vector pair/mma options on non-power10 systems. */
else if (!TARGET_POWER10 && TARGET_MMA)
{
@@ -5965,20 +5959,9 @@ num_insns_constant_gpr (HOST_WIDE_INT value)
&& (value >> 31 == -1 || value >> 31 == 0))
return 1;
- /* PADDI can support up to 34 bit signed integers, or using a combination of
- PADDI and shift left. */
- else if (TARGET_P10_LARGE_CONSTS)
- {
- if (SIGNED_INTEGER_34BIT_P (value))
- return 1;
-
- /* PLI and SLDI. */
- if ((value & 0xffffffff) == 0)
- return 2;
-
- /* PLI, SLDI, PADDI. */
- return 3;
- }
+ /* PADDI can support up to 34 bit signed integers. */
+ else if (TARGET_PREFIXED && SIGNED_INTEGER_34BIT_P (value))
+ return 1;
else if (TARGET_POWERPC64)
{
@@ -10432,31 +10415,7 @@ rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c)
rtx two = gen_rtx_ASHIFT (DImode, temp, GEN_INT (32));
emit_move_insn (dest, gen_rtx_IOR (DImode, one, two));
}
- /* We can't load R0 using PLI/SLDA/PADDI, since the R0 in the PADDI would be
- interpreted as 0 and not register 0. */
- else if (TARGET_P10_LARGE_CONSTS
- && (base_reg_operand (dest, DImode)
- || can_create_pseudo_p ()
- || (ud1 == 0 && ud2 == 0)))
- {
- HOST_WIDE_INT low_32bit = ud1 | (ud2 << 16);
- HOST_WIDE_INT high_32bit = ud3 | (ud4 << 16);
-
- temp = !can_create_pseudo_p () ? copy_rtx (dest) : gen_reg_rtx (DImode);
- emit_move_insn (temp, GEN_INT (high_32bit));
-
- if (!low_32bit)
- emit_insn (gen_ashldi3 (dest, temp, GEN_INT (32)));
- else
- {
- rtx temp2 = (!can_create_pseudo_p ()
- ? copy_rtx (dest)
- : gen_reg_rtx (DImode));
- emit_insn (gen_ashldi3 (temp2, temp, GEN_INT (32)));
- emit_insn (gen_adddi3 (dest, temp2, GEN_INT (low_32bit)));
- }
- }
- else if ((ud4 == 0xaffff && (ud3 & 0x8000))
+ else if ((ud4 == 0xffff && (ud3 & 0x8000))
|| (ud4 == 0 && ! (ud3 & 0x8000)))
{
temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
@@ -24465,7 +24424,6 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
{ "power9-misc", OPTION_MASK_P9_MISC, false, true },
{ "power9-vector", OPTION_MASK_P9_VECTOR, false, true },
{ "power10-fusion", OPTION_MASK_P10_FUSION, false, true },
- { "power10-large-consts", OPTION_MASK_P10_LARGE_CONSTS, false, true },
{ "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT, false, true },
{ "powerpc-gpopt", OPTION_MASK_PPC_GPOPT, false, true },
{ "prefixed", OPTION_MASK_PREFIXED, false, true },
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index add22c8be1a..e65dd8762a4 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -655,7 +655,3 @@ Generate (do not generate) XXSPLTI32DX instructions.
mlxvkq
Target Undocumented Mask(LXVKQ) Var(rs6000_isa_flags)
Generate (do not generate) LXVKQ instructions.
-
-mpower10-large-consts
-Target Undocumented Mask(P10_LARGE_CONSTS) Var(rs6000_isa_flags)
-Generate (do not generate) PLI/SLDI/PADDI to load large constants.
diff --git a/gcc/testsuite/gcc.target/powerpc/prefix-large-const.c b/gcc/testsuite/gcc.target/powerpc/prefix-large-const.c
deleted file mode 100644
index f13812cbc27..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/prefix-large-const.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target powerpc_prefixed_addr } */
-/* { dg-require-effective-target lp64 } */
-/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
-
-/* Test whether we can use PLI/PADDI to load up large constants. */
-
-long
-foo_1 (void)
-{
- return 1L << 53; /* LIS, SLDI. */
-}
-
-long
-foo_2 (void)
-{
- return (1L << 53) | (1L << 35); /* PLI, SLDI. */
-}
-
-long
-foo_3 (void)
-{
- return ((1L << 53) /* PLI, SLDI, PADDI. */
- | (1L << 35)
- | (1L << 30)
- | (1L << 2);
-}
-
-/* { dg-final { scan-assembler-times {\mlis\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mpaddi\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mpli\M} 2 } } */
-/* { dg-final { scan-assembler-times {\msldi\M} 3 } } */
^ permalink raw reply [flat|nested] 15+ messages in thread
* [gcc(refs/users/meissner/heads/work055)] Revert patch.
@ 2021-06-10 20:35 Michael Meissner
0 siblings, 0 replies; 15+ messages in thread
From: Michael Meissner @ 2021-06-10 20:35 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:a6dd1a6f6f07b6e43b60a0183645ee4599303255
commit a6dd1a6f6f07b6e43b60a0183645ee4599303255
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Jun 10 16:35:21 2021 -0400
Revert patch.
gcc/
2021-06-10 Michael Meissner <meissner@linux.ibm.com>
Revert patch.
PR target/101019
* config/rs6000/rs6000-cpus.def (ISA_3_1_MASKS_SERVER): Add
-mpower10-large-consts support.
(POWERPC_MASKS): Add -mpower10-large-consts support.
* config/rs6000/rs6000.c (rs6000_option_override_internal): Add
-mpower10-large-consts support.
(num_insns_constant_gpr): Add -mpower10-large-consts support.
(rs6000_emit_set_long_const): Add -mpower10-large-consts support.
(rs6000_opt_masks): Add -mpower10-large-consts.
* config/rs6000/rs6000.opt (-mpower10-large-consts): New switch.
gcc/testsuite/
2021-06-09 Michael Meissner <meissner@linux.ibm.com>
Revert patch.
PR target/101019
* gcc.target/powerpc/prefix-large-const.c: New test.
Diff:
---
gcc/config/rs6000/rs6000-cpus.def | 2 -
gcc/config/rs6000/rs6000.c | 51 ++--------------------
gcc/config/rs6000/rs6000.opt | 4 --
.../gcc.target/powerpc/prefix-large-const.c | 32 --------------
4 files changed, 4 insertions(+), 85 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def
index b119f574e4c..c0d89434fcd 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -90,7 +90,6 @@
| OPTION_MASK_P10_FUSION_LOGADD \
| OPTION_MASK_P10_FUSION_ADDLOG \
| OPTION_MASK_P10_FUSION_2ADD \
- | OPTION_MASK_P10_LARGE_CONSTS \
| OPTION_MASK_XXSPLTI32DX \
| OPTION_MASK_XXSPLTIDP \
| OPTION_MASK_XXSPLTIW)
@@ -146,7 +145,6 @@
| OPTION_MASK_P10_FUSION_LOGADD \
| OPTION_MASK_P10_FUSION_ADDLOG \
| OPTION_MASK_P10_FUSION_2ADD \
- | OPTION_MASK_P10_LARGE_CONSTS \
| OPTION_MASK_HTM \
| OPTION_MASK_ISEL \
| OPTION_MASK_LXVKQ \
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index d51c0ad13d4..ca92ee63d73 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -4489,12 +4489,6 @@ rs6000_option_override_internal (bool global_init_p)
&& (rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION_2ADD) == 0)
rs6000_isa_flags |= OPTION_MASK_P10_FUSION_2ADD;
- if (TARGET_PREFIXED
- && (rs6000_isa_flags_explicit & OPTION_MASK_P10_LARGE_CONSTS) == 0)
- rs6000_isa_flags |= OPTION_MASK_P10_LARGE_CONSTS;
- else if (!TARGET_PREFIXED)
- rs6000_isa_flags &= ~OPTION_MASK_P10_LARGE_CONSTS;
-
/* Turn off vector pair/mma options on non-power10 systems. */
else if (!TARGET_POWER10 && TARGET_MMA)
{
@@ -5965,20 +5959,9 @@ num_insns_constant_gpr (HOST_WIDE_INT value)
&& (value >> 31 == -1 || value >> 31 == 0))
return 1;
- /* PADDI can support up to 34 bit signed integers, or using a combination of
- PADDI and shift left. */
- else if (TARGET_P10_LARGE_CONSTS)
- {
- if (SIGNED_INTEGER_34BIT_P (value))
- return 1;
-
- /* PLI and SLDI. */
- if ((value & 0xffffffff) == 0)
- return 2;
-
- /* PLI, SLDI, PADDI. */
- return 3;
- }
+ /* PADDI can support up to 34 bit signed integers. */
+ else if (TARGET_PREFIXED && SIGNED_INTEGER_34BIT_P (value))
+ return 1;
else if (TARGET_POWERPC64)
{
@@ -10383,7 +10366,6 @@ rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c)
rtx temp;
HOST_WIDE_INT ud1, ud2, ud3, ud4;
- HOST_WIDE_INT orig_c = c;
ud1 = c & 0xffff;
c = c >> 16;
ud2 = c & 0xffff;
@@ -10433,31 +10415,7 @@ rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c)
rtx two = gen_rtx_ASHIFT (DImode, temp, GEN_INT (32));
emit_move_insn (dest, gen_rtx_IOR (DImode, one, two));
}
- /* We can't load R0 using PLI/SLDA/PADDI, since the R0 in the PADDI would be
- interpreted as 0 and not register 0. */
- else if (TARGET_P10_LARGE_CONSTS
- && (base_reg_operand (dest, DImode)
- || can_create_pseudo_p ()
- || (ud1 == 0 && ud2 == 0)))
- {
- HOST_WIDE_INT low_32bit = ud1 | (ud2 << 16);
- HOST_WIDE_INT high_32bit = ud3 | (ud4 << 16);
-
- temp = !can_create_pseudo_p () ? copy_rtx (dest) : gen_reg_rtx (DImode);
- emit_move_insn (temp, GEN_INT (high_32bit));
-
- if (!low_32bit)
- emit_insn (gen_ashldi3 (dest, temp, GEN_INT (32)));
- else
- {
- rtx temp2 = (!can_create_pseudo_p ()
- ? copy_rtx (dest)
- : gen_reg_rtx (DImode));
- emit_insn (gen_ashldi3 (temp2, temp, GEN_INT (32)));
- emit_insn (gen_adddi3 (dest, temp2, GEN_INT (low_32bit)));
- }
- }
- else if ((ud4 == 0xaffff && (ud3 & 0x8000))
+ else if ((ud4 == 0xffff && (ud3 & 0x8000))
|| (ud4 == 0 && ! (ud3 & 0x8000)))
{
temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
@@ -24466,7 +24424,6 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
{ "power9-misc", OPTION_MASK_P9_MISC, false, true },
{ "power9-vector", OPTION_MASK_P9_VECTOR, false, true },
{ "power10-fusion", OPTION_MASK_P10_FUSION, false, true },
- { "power10-large-consts", OPTION_MASK_P10_LARGE_CONSTS, false, true },
{ "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT, false, true },
{ "powerpc-gpopt", OPTION_MASK_PPC_GPOPT, false, true },
{ "prefixed", OPTION_MASK_PREFIXED, false, true },
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index add22c8be1a..e65dd8762a4 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -655,7 +655,3 @@ Generate (do not generate) XXSPLTI32DX instructions.
mlxvkq
Target Undocumented Mask(LXVKQ) Var(rs6000_isa_flags)
Generate (do not generate) LXVKQ instructions.
-
-mpower10-large-consts
-Target Undocumented Mask(P10_LARGE_CONSTS) Var(rs6000_isa_flags)
-Generate (do not generate) PLI/SLDI/PADDI to load large constants.
diff --git a/gcc/testsuite/gcc.target/powerpc/prefix-large-const.c b/gcc/testsuite/gcc.target/powerpc/prefix-large-const.c
deleted file mode 100644
index f13812cbc27..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/prefix-large-const.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target powerpc_prefixed_addr } */
-/* { dg-require-effective-target lp64 } */
-/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
-
-/* Test whether we can use PLI/PADDI to load up large constants. */
-
-long
-foo_1 (void)
-{
- return 1L << 53; /* LIS, SLDI. */
-}
-
-long
-foo_2 (void)
-{
- return (1L << 53) | (1L << 35); /* PLI, SLDI. */
-}
-
-long
-foo_3 (void)
-{
- return ((1L << 53) /* PLI, SLDI, PADDI. */
- | (1L << 35)
- | (1L << 30)
- | (1L << 2);
-}
-
-/* { dg-final { scan-assembler-times {\mlis\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mpaddi\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mpli\M} 2 } } */
-/* { dg-final { scan-assembler-times {\msldi\M} 3 } } */
^ permalink raw reply [flat|nested] 15+ messages in thread
* [gcc(refs/users/meissner/heads/work055)] Revert patch.
@ 2021-06-10 17:03 Michael Meissner
0 siblings, 0 replies; 15+ messages in thread
From: Michael Meissner @ 2021-06-10 17:03 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:9bbd89f28e871ed829f788ddafe7c059747aa051
commit 9bbd89f28e871ed829f788ddafe7c059747aa051
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Jun 10 13:02:35 2021 -0400
Revert patch.
gcc/
2021-06-10 Michael Meissner <meissner@linux.ibm.com>
Revert patch.
PR target/101019
* config/rs6000/rs6000-cpus.def (ISA_3_1_MASKS_SERVER): Add
-mpower10-large-consts support.
(POWERPC_MASKS): Add -mpower10-large-consts support.
* config/rs6000/rs6000.c (rs6000_option_override_internal): Add
-mpower10-large-consts support.
(num_insns_constant_gpr): Add -mpower10-large-consts support.
(rs6000_emit_set_long_const): Add -mpower10-large-consts support.
(rs6000_opt_masks): Add -mpower10-large-consts.
* config/rs6000/rs6000.opt (-mpower10-large-consts): New switch.
gcc/testsuite/
2021-06-09 Michael Meissner <meissner@linux.ibm.com>
Revert patch.
PR target/101019
* gcc.target/powerpc/prefix-large-const.c: New test.
Diff:
---
gcc/config/rs6000/rs6000-cpus.def | 2 --
gcc/config/rs6000/rs6000.c | 41 +++-------------------
gcc/config/rs6000/rs6000.opt | 4 ---
.../gcc.target/powerpc/prefix-large-const.c | 32 -----------------
4 files changed, 4 insertions(+), 75 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def
index b119f574e4c..c0d89434fcd 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -90,7 +90,6 @@
| OPTION_MASK_P10_FUSION_LOGADD \
| OPTION_MASK_P10_FUSION_ADDLOG \
| OPTION_MASK_P10_FUSION_2ADD \
- | OPTION_MASK_P10_LARGE_CONSTS \
| OPTION_MASK_XXSPLTI32DX \
| OPTION_MASK_XXSPLTIDP \
| OPTION_MASK_XXSPLTIW)
@@ -146,7 +145,6 @@
| OPTION_MASK_P10_FUSION_LOGADD \
| OPTION_MASK_P10_FUSION_ADDLOG \
| OPTION_MASK_P10_FUSION_2ADD \
- | OPTION_MASK_P10_LARGE_CONSTS \
| OPTION_MASK_HTM \
| OPTION_MASK_ISEL \
| OPTION_MASK_LXVKQ \
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 47703fbb2fe..ca92ee63d73 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -4489,12 +4489,6 @@ rs6000_option_override_internal (bool global_init_p)
&& (rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION_2ADD) == 0)
rs6000_isa_flags |= OPTION_MASK_P10_FUSION_2ADD;
- if (TARGET_PREFIXED
- && (rs6000_isa_flags_explicit & OPTION_MASK_P10_LARGE_CONSTS) == 0)
- rs6000_isa_flags |= OPTION_MASK_P10_LARGE_CONSTS;
- else if (!TARGET_PREFIXED)
- rs6000_isa_flags &= ~OPTION_MASK_P10_LARGE_CONSTS;
-
/* Turn off vector pair/mma options on non-power10 systems. */
else if (!TARGET_POWER10 && TARGET_MMA)
{
@@ -5965,20 +5959,9 @@ num_insns_constant_gpr (HOST_WIDE_INT value)
&& (value >> 31 == -1 || value >> 31 == 0))
return 1;
- /* PADDI can support up to 34 bit signed integers, or using a combination of
- PADDI and shift left. */
- else if (TARGET_P10_LARGE_CONSTS)
- {
- if (SIGNED_INTEGER_34BIT_P (value))
- return 1;
-
- /* PLI and SLDI. */
- if ((value & 0xffffffff) == 0)
- return 2;
-
- /* PLI, SLDI, PADDI. */
- return 3;
- }
+ /* PADDI can support up to 34 bit signed integers. */
+ else if (TARGET_PREFIXED && SIGNED_INTEGER_34BIT_P (value))
+ return 1;
else if (TARGET_POWERPC64)
{
@@ -10432,22 +10415,7 @@ rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c)
rtx two = gen_rtx_ASHIFT (DImode, temp, GEN_INT (32));
emit_move_insn (dest, gen_rtx_IOR (DImode, one, two));
}
- else if (TARGET_P10_LARGE_CONSTS)
- {
- HOST_WIDE_INT low_32bit = ud1 | (ud2 << 16);
- HOST_WIDE_INT high_32bit = ud3 | (ud4 << 16);
-
- temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
- emit_move_insn (copy_rtx (temp), GEN_INT (high_32bit));
-
- rtx temp2 = ((low_32bit == 0 || !can_create_pseudo_p ())
- ? dest
- : gen_reg_rtx (DImode));
- emit_insn (gen_ashldi3 (temp2, temp, GEN_INT (32)));
- if (low_32bit)
- emit_insn (gen_adddi3 (dest, temp2, GEN_INT (low_32bit)));
- }
- else if ((ud4 == 0xaffff && (ud3 & 0x8000))
+ else if ((ud4 == 0xffff && (ud3 & 0x8000))
|| (ud4 == 0 && ! (ud3 & 0x8000)))
{
temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
@@ -24456,7 +24424,6 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
{ "power9-misc", OPTION_MASK_P9_MISC, false, true },
{ "power9-vector", OPTION_MASK_P9_VECTOR, false, true },
{ "power10-fusion", OPTION_MASK_P10_FUSION, false, true },
- { "power10-large-consts", OPTION_MASK_P10_LARGE_CONSTS, false, true },
{ "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT, false, true },
{ "powerpc-gpopt", OPTION_MASK_PPC_GPOPT, false, true },
{ "prefixed", OPTION_MASK_PREFIXED, false, true },
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index add22c8be1a..e65dd8762a4 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -655,7 +655,3 @@ Generate (do not generate) XXSPLTI32DX instructions.
mlxvkq
Target Undocumented Mask(LXVKQ) Var(rs6000_isa_flags)
Generate (do not generate) LXVKQ instructions.
-
-mpower10-large-consts
-Target Undocumented Mask(P10_LARGE_CONSTS) Var(rs6000_isa_flags)
-Generate (do not generate) PLI/SLDI/PADDI to load large constants.
diff --git a/gcc/testsuite/gcc.target/powerpc/prefix-large-const.c b/gcc/testsuite/gcc.target/powerpc/prefix-large-const.c
deleted file mode 100644
index f13812cbc27..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/prefix-large-const.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target powerpc_prefixed_addr } */
-/* { dg-require-effective-target lp64 } */
-/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
-
-/* Test whether we can use PLI/PADDI to load up large constants. */
-
-long
-foo_1 (void)
-{
- return 1L << 53; /* LIS, SLDI. */
-}
-
-long
-foo_2 (void)
-{
- return (1L << 53) | (1L << 35); /* PLI, SLDI. */
-}
-
-long
-foo_3 (void)
-{
- return ((1L << 53) /* PLI, SLDI, PADDI. */
- | (1L << 35)
- | (1L << 30)
- | (1L << 2);
-}
-
-/* { dg-final { scan-assembler-times {\mlis\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mpaddi\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mpli\M} 2 } } */
-/* { dg-final { scan-assembler-times {\msldi\M} 3 } } */
^ permalink raw reply [flat|nested] 15+ messages in thread
* [gcc(refs/users/meissner/heads/work055)] Revert patch.
@ 2021-06-09 17:48 Michael Meissner
0 siblings, 0 replies; 15+ messages in thread
From: Michael Meissner @ 2021-06-09 17:48 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:c7b5510003c3834360dc842e5ffadf57678981e9
commit c7b5510003c3834360dc842e5ffadf57678981e9
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Jun 9 13:47:52 2021 -0400
Revert patch.
gcc/
2021-06-09 Michael Meissner <meissner@linux.ibm.com>
Revert patch.
PR target/99293
* config/rs6000/vsx.md (vsx_splat_extract_<mode): New insn.
Diff:
---
gcc/config/rs6000/vsx.md | 18 ------------------
1 file changed, 18 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 008ffbe5366..bc708113865 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4515,24 +4515,6 @@
"lxvdsx %x0,%y1"
[(set_attr "type" "vecload")])
-;; Optimize SPLAT of an extract from a V2DF/V2DI vector with a constant element
-(define_insn "*vsx_splat_extract_<mode>"
- [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wa")
- (vec_duplicate:VSX_D
- (vec_select:<VS_scalar>
- (match_operand:VSX_D 1 "vsx_register_operand" "wa")
- (parallel [(match_operand 2 "const_0_to_1_operand" "n")]))))]
- "VECTOR_MEM_VSX_P (<MODE>mode)"
-{
- int which_word = INTVAL (operands[2]);
- if (!BYTES_BIG_ENDIAN)
- which_word = 1 - which_word;
-
- operands[3] = GEN_INT (which_word ? 3 : 0);
- return "xxpermdi %x0,%x1,%x1,%3";
-}
- [(set_attr "type" "vecperm")])
-
;; V4SI splat support
(define_insn "vsx_splat_v4si"
[(set (match_operand:V4SI 0 "vsx_register_operand" "=we,we")
^ permalink raw reply [flat|nested] 15+ messages in thread
* [gcc(refs/users/meissner/heads/work055)] Revert patch.
@ 2021-06-09 15:45 Michael Meissner
0 siblings, 0 replies; 15+ messages in thread
From: Michael Meissner @ 2021-06-09 15:45 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:92301d99f85ac94c0712939766fc0054b3e0fb7a
commit 92301d99f85ac94c0712939766fc0054b3e0fb7a
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Jun 9 11:44:31 2021 -0400
Revert patch.
gcc/
2021-06-09 Michael Meissner <meissner@linux.ibm.com>
Revert patch.
* config/rs6000/predicates.md (xxspltiw_operand): New predicate.
(easy_vector_constant): If we can use XXSPLTIW, the vector
constant is easy.
* config/rs6000/rs6000-cpus.def (ISA_3_1_MASKS_SERVER): Add
-mxxspltiw support.
(POWERPC_MASKS): Add -mxxspltiw support.
* config/rs6000/rs6000.c (rs6000_option_override_internal): Add
-mxxspltiw support.
(xxspltib_constant_p): If we can generate XXSPLTIW, don't generate
a XXSPLTIB and an extend instruction.
(output_vec_const_move): Add support for loading up vector
constants with XXSPLTIW.
(rs6000_opt_masks): Add -mxxspltiw.
* config/rs6000/rs6000.h (SIGN_EXTEND_8BIT): New macro.
(SIGN_EXTEND_16BIT): New macro.
(SIGN_EXTEND_32BIT): New macro.
* config/rs6000/rs6000.opt (-mxxspltiw): New debug switch.
* config/rs6000/vsx.md (UNSPEC_XXSPLTIW): Delete.
(xxspltiw_v8hi): New insn.
(xxspltiw_v4si): Rewrite to generate a vector constant.
(xxspltiw_v4sf): Rewrite to generate a vector constant.
(xxspltiw_v4si_inst): Delete.
(xxspltiw_v4sf_inst): Delete.
(xxspltiw_v8hi_dup): New insn.
(xxspltiw_v4si_dup): New insn.
(xxspltiw_v4sf_dup): New insn.
(XXSPLTIW): New mode iterator.
(XXSPLTIW splitter): New insn splitter for XXSPLTIW.
gcc/testsuite/
2021-06-09 Michael Meissner <meissner@linux.ibm.com>
* gcc.target/powerpc/vec-splati-runnable.c: Update insn counts.
* gcc.target/powerpc/vec-splat-constant-v4sf.c: New test.
* gcc.target/powerpc/vec-splat-constant-v4si.c: New test.
* gcc.target/powerpc/vec-splat-constant-v8hi.c: New test.
Diff:
---
gcc/config/rs6000/predicates.md | 29 ----
gcc/config/rs6000/rs6000-cpus.def | 7 +-
gcc/config/rs6000/rs6000.c | 18 +--
gcc/config/rs6000/rs6000.h | 19 ---
gcc/config/rs6000/rs6000.opt | 4 -
gcc/config/rs6000/vsx.md | 146 +++++----------------
.../gcc.target/powerpc/vec-splat-constant-v4sf.c | 66 ----------
.../gcc.target/powerpc/vec-splat-constant-v4si.c | 51 -------
.../gcc.target/powerpc/vec-splat-constant-v8hi.c | 53 --------
.../gcc.target/powerpc/vec-splati-runnable.c | 4 +-
10 files changed, 40 insertions(+), 357 deletions(-)
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index aa17ddc94e5..121cbf14810 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -640,32 +640,6 @@
return num_insns == 1;
})
-;; Return 1 if the operand is a CONST_VECTOR that can be loaded with the
-;; XXSPLTIW instruction. Do not return 1 if the constant can be generated with
-;; XXSPLTIB or VSPLTIS{H,W}
-(define_predicate "xxspltiw_operand"
- (match_code "const_vector")
-{
- if (!TARGET_XXSPLTIW)
- return false;
-
- if (mode != V8HImode && mode != V4SImode && mode != V4SFmode)
- return false;
-
- rtx element = CONST_VECTOR_ELT (op, 0);
- for (size_t i = 1; i < GET_MODE_NUNITS (mode); i++)
- if (!rtx_equal_p (element, CONST_VECTOR_ELT (op, i)))
- return false;
-
- if (element == CONST0_RTX (GET_MODE_INNER (mode)))
- return false;
-
- if (CONST_INT_P (element) && EASY_VECTOR_15 (INTVAL (element)))
- return false;
-
- return true;
-})
-
;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a
;; vector register without using memory.
(define_predicate "easy_vector_constant"
@@ -679,9 +653,6 @@
if (zero_constant (op, mode) || all_ones_constant (op, mode))
return true;
- if (xxspltiw_operand (op, mode))
- return true;
-
if (TARGET_P9_VECTOR
&& xxspltib_constant_p (op, mode, &num_insns, &value))
return true;
diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def
index e6c5891d334..52ce84835f7 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -88,8 +88,7 @@
| OPTION_MASK_P10_FUSION_2LOGICAL \
| OPTION_MASK_P10_FUSION_LOGADD \
| OPTION_MASK_P10_FUSION_ADDLOG \
- | OPTION_MASK_P10_FUSION_2ADD \
- | OPTION_MASK_XXSPLTIW)
+ | OPTION_MASK_P10_FUSION_2ADD)
/* Flags that need to be turned off if -mno-power9-vector. */
#define OTHER_P9_VECTOR_MASKS (OPTION_MASK_FLOAT128_HW \
@@ -167,8 +166,8 @@
| OPTION_MASK_RECIP_PRECISION \
| OPTION_MASK_SOFT_FLOAT \
| OPTION_MASK_STRICT_ALIGN_OPTIONAL \
- | OPTION_MASK_VSX \
- | OPTION_MASK_XXSPLTIW)
+ | OPTION_MASK_VSX)
+
#endif
/* This table occasionally claims that a processor does not support a
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 2ac53d74a77..9bb945de7bb 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -4501,12 +4501,6 @@ rs6000_option_override_internal (bool global_init_p)
if (!TARGET_PCREL && TARGET_PCREL_OPT)
rs6000_isa_flags &= ~OPTION_MASK_PCREL_OPT;
- if (TARGET_POWER10 && TARGET_VSX
- && (rs6000_isa_flags_explicit & OPTION_MASK_XXSPLTIW) == 0)
- rs6000_isa_flags |= OPTION_MASK_XXSPLTIW;
- else if (!TARGET_POWER10 || !TARGET_VSX)
- rs6000_isa_flags &= ~OPTION_MASK_XXSPLTIW;
-
if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
rs6000_print_isa_options (stderr, 0, "after subtarget", rs6000_isa_flags);
@@ -6488,11 +6482,9 @@ xxspltib_constant_p (rtx op,
/* See if we could generate vspltisw/vspltish directly instead of xxspltib +
sign extend. Special case 0/-1 to allow getting any VSX register instead
- of an Altivec register. Also if we can generate a XXSPLTIW instruction,
- don't emit a XXSPLTIB and an extend instruction. */
- if ((mode == V4SImode || mode == V8HImode)
- && !IN_RANGE (value, -1, 0)
- && (EASY_VECTOR_15 (value) || TARGET_XXSPLTIW))
+ of an Altivec register. */
+ if ((mode == V4SImode || mode == V8HImode) && !IN_RANGE (value, -1, 0)
+ && EASY_VECTOR_15 (value))
return false;
/* Return # of instructions and the constant byte for XXSPLTIB. */
@@ -6553,9 +6545,6 @@ output_vec_const_move (rtx *operands)
gcc_unreachable ();
}
- if (xxspltiw_operand (vec, mode))
- return "#";
-
if (TARGET_P9_VECTOR
&& xxspltib_constant_p (vec, mode, &num_insns, &xxspltib_value))
{
@@ -24127,7 +24116,6 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
{ "string", 0, false, true },
{ "update", OPTION_MASK_NO_UPDATE, true , true },
{ "vsx", OPTION_MASK_VSX, false, true },
- { "xxspltiw", OPTION_MASK_XXSPLTIW, false, true },
#ifdef OPTION_MASK_64BIT
#if TARGET_AIX_OS
{ "aix64", OPTION_MASK_64BIT, false, false },
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index e03f14a0405..7131de609e3 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -2612,22 +2612,3 @@ while (0)
rs6000_asm_output_opcode (STREAM); \
} \
while (0)
-
-/* Provide macros for sign-extending values. */
-#if HOST_BITS_PER_CHAR == 8
-#define SIGN_EXTEND_8BIT(X) ((HOST_WIDE_INT)(signed char)(X))
-#else
-#define SIGN_EXTEND_8BIT(X) ((((X) & 0xff) ^ 0x80) - 0x80)
-#endif
-
-#if HOST_BITS_PER_SHORT == 16
-#define SIGN_EXTEND_16BIT(X) ((HOST_WIDE_INT)(short)(X))
-#else
-#define SIGN_EXTEND_16BIT(X) ((((X) & 0xffff) ^ 0x8000) - 0x8000)
-#endif
-
-#if HOST_BITS_PER_INT == 32
-#define SIGN_EXTEND_32BIT(X) ((HOST_WIDE_INT)(int)(X))
-#else
-#define SIGN_EXTEND_32BIT(X) ((((X) & 0xffffffff) ^ 0x80000000) - 0x80000000)
-#endif
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 38eaa36d6d8..0538db387dc 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -639,7 +639,3 @@ Enable instructions that guard against return-oriented programming attacks.
mprivileged
Target Var(rs6000_privileged) Init(0)
Generate code that will run in privileged state.
-
-mxxspltiw
-Target Undocumented Mask(XXSPLTIW) Var(rs6000_isa_flags)
-Generate (do not generate) XXSPLTIW instructions.
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 76e10f73dec..15a8c0e22d8 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -386,6 +386,7 @@
UNSPEC_VDIVES
UNSPEC_VDIVEU
UNSPEC_XXEVAL
+ UNSPEC_XXSPLTIW
UNSPEC_XXSPLTID
UNSPEC_XXSPLTI32DX
UNSPEC_XXBLEND
@@ -6238,6 +6239,36 @@
"vmulld %0,%1,%2"
[(set_attr "type" "veccomplex")])
+;; XXSPLTIW built-in function support
+(define_insn "xxspltiw_v4si"
+ [(set (match_operand:V4SI 0 "register_operand" "=wa")
+ (unspec:V4SI [(match_operand:SI 1 "s32bit_cint_operand" "n")]
+ UNSPEC_XXSPLTIW))]
+ "TARGET_POWER10"
+ "xxspltiw %x0,%1"
+ [(set_attr "type" "vecsimple")
+ (set_attr "prefixed" "yes")])
+
+(define_expand "xxspltiw_v4sf"
+ [(set (match_operand:V4SF 0 "register_operand" "=wa")
+ (unspec:V4SF [(match_operand:SF 1 "const_double_operand" "n")]
+ UNSPEC_XXSPLTIW))]
+ "TARGET_POWER10"
+{
+ long long value = rs6000_const_f32_to_i32 (operands[1]);
+ emit_insn (gen_xxspltiw_v4sf_inst (operands[0], GEN_INT (value)));
+ DONE;
+})
+
+(define_insn "xxspltiw_v4sf_inst"
+ [(set (match_operand:V4SF 0 "register_operand" "=wa")
+ (unspec:V4SF [(match_operand:SI 1 "c32bit_cint_operand" "n")]
+ UNSPEC_XXSPLTIW))]
+ "TARGET_POWER10"
+ "xxspltiw %x0,%1"
+ [(set_attr "type" "vecsimple")
+ (set_attr "prefixed" "yes")])
+
;; XXSPLTIDP built-in function support
(define_expand "xxspltidp_v2df"
[(set (match_operand:V2DF 0 "register_operand" )
@@ -6389,118 +6420,3 @@
[(set_attr "type" "vecsimple")
(set_attr "prefixed" "yes")])
-;; XXSPLTIW built-in function support. Convert to a vector constant, which
-;; will then be optimized to the XXSPLTIW instruction.
-(define_expand "xxspltiw_v4si"
- [(use (match_operand:V4SI 0 "register_operand"))
- (use (match_operand:SI 1 "s32bit_cint_operand"))]
- "TARGET_POWER10"
-{
- rtx op1 = operands[1];
- rtvec rv = gen_rtvec (4, op1, op1, op1, op1);
- rtx vec_constant = gen_rtx_CONST_VECTOR (V4SImode, rv);
- emit_move_insn (operands[0], vec_constant);
-})
-
-(define_expand "xxspltiw_v4sf"
- [(use (match_operand:V4SF 0 "register_operand"))
- (use (match_operand:SF 1 "const_double_operand"))]
- "TARGET_POWER10"
-{
- rtx op1 = operands[1];
- rtvec rv = gen_rtvec (4, op1, op1, op1, op1);
- rtx vec_constant = gen_rtx_CONST_VECTOR (V4SFmode, rv);
- emit_move_insn (operands[0], vec_constant);
-})
-
-;; XXSPLTIW support. Add support for the XXSPLTIW built-in functions, and to
-;; use XXSPLTIW to load up vector V8HImode, V4SImode, and V4SFmode vector
-;; constants where all elements are the the same. We special case loading up
-;; integer -16..15 and floating point 0.0f, since we can use the shorter
-;; XXSPLTIB, VSPLTISH, and VSPLTISW instructions.
-
-(define_insn "*xxspltiw_v8hi_dup"
- [(set (match_operand:V8HI 0 "vsx_register_operand" "=wa,wa,v,wa")
- (vec_duplicate:V8HI
- (match_operand 1 "const_int_operand" "O,wM,wB,n")))]
- "TARGET_XXSPLTIW"
-{
- HOST_WIDE_INT sign_value = SIGN_EXTEND_16BIT (INTVAL (operands[1]));
-
- if (sign_value == 0)
- return "xxspltib %x0,0";
-
- if (sign_value == -1)
- return "xxspltib %x0,255";
-
- int r = reg_or_subregno (operands[0]);
- if (ALTIVEC_REGNO_P (r) && EASY_VECTOR_15 (sign_value))
- {
- operands[2] = GEN_INT (sign_value);
- return "vspltish %0,%1";
- }
-
- HOST_WIDE_INT uns_value = sign_value & 0xffff;
- operands[2] = GEN_INT ((uns_value << 16) | uns_value);
- return "xxspltiw %x0,%2";
-}
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "*,*,*,yes")])
-
-(define_insn "*xxspltiw_v4si_dup"
- [(set (match_operand:V4SI 0 "vsx_register_operand" "=wa,wa,v,wa")
- (vec_duplicate:V4SI
- (match_operand 1 "const_int_operand" "O,wM,wB,n")))]
- "TARGET_XXSPLTIW"
-{
- HOST_WIDE_INT sign_value = SIGN_EXTEND_32BIT (INTVAL (operands[1]));
-
- if (sign_value == 0)
- return "xxspltib %x0,0";
-
- if (sign_value == -1)
- return "xxspltib %x0,255";
-
- int r = reg_or_subregno (operands[0]);
- if (ALTIVEC_REGNO_P (r) && EASY_VECTOR_15 (sign_value))
- {
- operands[2] = GEN_INT (sign_value);
- return "vspltisw %0,%2";
- }
-
- /* The assembler doesn't like negative values. */
- operands[2] = GEN_INT (sign_value & 0xffffffff);
- return "xxspltiw %x0,%2";
-}
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "*,*,*,yes")])
-
-(define_insn "xxspltiw_v4sf_dup"
- [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,wa")
- (vec_duplicate:V4SF
- (match_operand:SF 1 "const_double_operand" "O,F")))]
- "TARGET_XXSPLTIW"
-{
- if (operands[1] == CONST0_RTX (SFmode))
- return "xxspltib %x0,0";
-
- /* The assembler doesn't like negative values. */
- long value = rs6000_const_f32_to_i32 (operands[1]);
- operands[2] = GEN_INT (value & 0xffffffff);
- return "xxspltiw %x0,%2";
-}
- [(set_attr "type" "vecsimple")
- (set_attr "prefixed" "*,yes")])
-
-;; Convert vector constant to vec_duplicate.
-(define_mode_iterator XXSPLTIW [V8HI V4SI V4SF])
-
-(define_split
- [(set (match_operand:XXSPLTIW 0 "vsx_register_operand")
- (match_operand:XXSPLTIW 1 "xxspltiw_operand"))]
- "TARGET_XXSPLTIW && GET_CODE (operands[1]) == CONST_VECTOR"
- [(set (match_dup 0)
- (vec_duplicate:<MODE> (match_dup 2)))]
-{
- operands[2] = CONST_VECTOR_ELT (operands[1], 0);
-})
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c
deleted file mode 100644
index 06830b02076..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V4SF vector constants. */
-
-vector float
-v4sf_const_1 (void)
-{
- return (vector float) { 1.0f, 1.0f, 1.0f, 1.0f }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_nan (void)
-{
- return (vector float) { __builtin_nanf (""),
- __builtin_nanf (""),
- __builtin_nanf (""),
- __builtin_nanf ("") }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_inf (void)
-{
- return (vector float) { __builtin_inff (),
- __builtin_inff (),
- __builtin_inff (),
- __builtin_inff () }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_m0 (void)
-{
- return (vector float) { -0.0f, -0.0f, -0.0f, -0.0f }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_splats_1 (void)
-{
- return vec_splats (1.0f); /* XXSPLTIW. */
-}
-
-vector float
-v4sf_splats_nan (void)
-{
- return vec_splats (__builtin_nanf ("")); /* XXSPLTIW. */
-}
-
-vector float
-v4sf_splats_inf (void)
-{
- return vec_splats (__builtin_inff ()); /* XXSPLTIW. */
-}
-
-vector float
-v8hi_splats_m0 (void)
-{
- return vec_splats (-0.0f); /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 8 } } */
-/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c
deleted file mode 100644
index 02d0c6d66a2..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V4SI vector constants. We make sure
- the power9 support (XXSPLTIB/VEXTSB2W) is not done. */
-
-vector int
-v4si_const_1 (void)
-{
- return (vector int) { 1, 1, 1, 1 }; /* VSLTPISW. */
-}
-
-vector int
-v4si_const_126 (void)
-{
- return (vector int) { 126, 126, 126, 126 }; /* XXSPLTIW. */
-}
-
-vector int
-v4si_const_1023 (void)
-{
- return (vector int) { 1023, 1023, 1023, 1023 }; /* XXSPLTIW. */
-}
-
-vector int
-v4si_splats_1 (void)
-{
- return vec_splats (1); /* VSLTPISW. */
-}
-
-vector int
-v4si_splats_126 (void)
-{
- return vec_splats (126); /* XXSPLTIW. */
-}
-
-vector int
-v8hi_splats_1023 (void)
-{
- return vec_splats (1023); /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mvspltisw\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */
-/* { dg-final { scan-assembler-not {\mvextsb2w\M} } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c
deleted file mode 100644
index e6d0fab6d67..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V8HI vector constants. We make sure
- the power9 support (XXSPLTIB/VUPKLSB) is not done. */
-
-vector short
-v8hi_const_1 (void)
-{
- return (vector short) { 1, 1, 1, 1, 1, 1, 1, 1 }; /* VSLTPISH. */
-}
-
-vector short
-v8hi_const_126 (void)
-{
- return (vector short) { 126, 126, 126, 126,
- 126, 126, 126, 126 }; /* XXSPLTIW. */
-}
-
-vector short
-v8hi_const_1023 (void)
-{
- return (vector short) { 1023, 1023, 1023, 1023,
- 1023, 1023, 1023, 1023 }; /* XXSPLTIW. */
-}
-
-vector short
-v8hi_splats_1 (void)
-{
- return vec_splats ((short)1); /* VSLTPISH. */
-}
-
-vector short
-v8hi_splats_126 (void)
-{
- return vec_splats ((short)126); /* XXSPLTIW. */
-}
-
-vector short
-v8hi_splats_1023 (void)
-{
- return vec_splats ((short)1023); /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mvspltish\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */
-/* { dg-final { scan-assembler-not {\mvupklsb\M} } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c b/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
index f49ef91422e..a135279b1d7 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
@@ -149,6 +149,8 @@ main (int argc, char *argv [])
return 0;
}
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mxxspltiw\M} 2 } } */
/* { dg-final { scan-assembler-times {\mxxspltidp\M} 2 } } */
/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 3 } } */
+
+
^ permalink raw reply [flat|nested] 15+ messages in thread
* [gcc(refs/users/meissner/heads/work055)] Revert patch.
@ 2021-06-09 6:04 Michael Meissner
0 siblings, 0 replies; 15+ messages in thread
From: Michael Meissner @ 2021-06-09 6:04 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:df30ae707583b88e176d887956bca608e010dcd8
commit df30ae707583b88e176d887956bca608e010dcd8
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Jun 9 02:03:51 2021 -0400
Revert patch.
gcc/testsuite/
2021-06-09 Michael Meissner <meissner@linux.ibm.com>
Revert patch.
PR testsuite/100167
* gcc.target/powerpc/fold-vec-div-longlong.c:
* gcc.target/powerpc/fold-vec-mult-longlong.c: Fix expected code
generation on power10.
Diff:
---
gcc/testsuite/gcc.target/powerpc/fold-vec-div-longlong.c | 7 ++-----
gcc/testsuite/gcc.target/powerpc/fold-vec-mult-longlong.c | 3 +--
2 files changed, 3 insertions(+), 7 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-div-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-div-longlong.c
index f6a9b290ae5..312e984d3cc 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-div-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-div-longlong.c
@@ -19,8 +19,5 @@ test6 (vector unsigned long long x, vector unsigned long long y)
{
return vec_div (x, y);
}
-
-/* { dg-final { scan-assembler-times {\mdivd\M} 2 { target { ! has_arch_pwr10 } } } } */
-/* { dg-final { scan-assembler-times {\mdivdu\M} 2 { target { ! has_arch_pwr10 } } } } */
-/* { dg-final { scan-assembler-times {\mvdivsd\M} 1 { target { has_arch_pwr10 } } } } */
-/* { dg-final { scan-assembler-times {\mvdivud\M} 1 { target { has_arch_pwr10 } } } } */
+/* { dg-final { scan-assembler-times {\mdivd\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mdivdu\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-longlong.c
index 8d26f508f48..38dba9f5023 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-longlong.c
@@ -20,6 +20,5 @@ test6 (vector unsigned long long x, vector unsigned long long y)
return vec_mul (x, y);
}
-/* { dg-final { scan-assembler-times {\mmulld\M} 4 { target { lp64 && { ! has_arch_pwr10 } } } } } */
-/* { dg-final { scan-assembler-times {\mvmulld\M} 1 { target { has_arch_pwr10 } } } } */
+/* { dg-final { scan-assembler-times "\[ \t\]mulld " 4 { target lp64 } } } */
^ permalink raw reply [flat|nested] 15+ messages in thread
* [gcc(refs/users/meissner/heads/work055)] Revert patch.
@ 2021-06-09 5:36 Michael Meissner
0 siblings, 0 replies; 15+ messages in thread
From: Michael Meissner @ 2021-06-09 5:36 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:398b2d87b96890aa87bf3f15b0365ac866739b2b
commit 398b2d87b96890aa87bf3f15b0365ac866739b2b
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Jun 9 01:36:21 2021 -0400
Revert patch.
gcc/testsuite/
2021-06-09 Michael Meissner <meissner@linux.ibm.com>
Revert patch.
PR testsuite/100167
* gcc.target/powerpc/fold-vec-div-longlong.c:
* gcc.target/powerpc/fold-vec-mult-longlong.c: Fix expected code
generation on power10.
Diff:
---
gcc/testsuite/gcc.target/powerpc/fold-vec-div-longlong.c | 7 ++-----
gcc/testsuite/gcc.target/powerpc/fold-vec-mult-longlong.c | 3 +--
2 files changed, 3 insertions(+), 7 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-div-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-div-longlong.c
index 8a64814afa0..312e984d3cc 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-div-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-div-longlong.c
@@ -19,8 +19,5 @@ test6 (vector unsigned long long x, vector unsigned long long y)
{
return vec_div (x, y);
}
-
-/* { dg-final { scan-assembler-times {\mdivd\M} 2 { target { !has_arch_pwr10 } } } } */
-/* { dg-final { scan-assembler-times {\mdivdu\M} 2 { target { !has_arch_pwr10 } } } } */
-/* { dg-final { scan-assembler-times {\mvdivsd\M} 1 { target { has_arch_pwr10 } } } } */
-/* { dg-final { scan-assembler-times {\mvdivud\M} 1 { target { has_arch_pwr10 } } } } */
+/* { dg-final { scan-assembler-times {\mdivd\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mdivdu\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-longlong.c
index 8d26f508f48..38dba9f5023 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-longlong.c
@@ -20,6 +20,5 @@ test6 (vector unsigned long long x, vector unsigned long long y)
return vec_mul (x, y);
}
-/* { dg-final { scan-assembler-times {\mmulld\M} 4 { target { lp64 && { ! has_arch_pwr10 } } } } } */
-/* { dg-final { scan-assembler-times {\mvmulld\M} 1 { target { has_arch_pwr10 } } } } */
+/* { dg-final { scan-assembler-times "\[ \t\]mulld " 4 { target lp64 } } } */
^ permalink raw reply [flat|nested] 15+ messages in thread
* [gcc(refs/users/meissner/heads/work055)] Revert patch.
@ 2021-06-09 5:32 Michael Meissner
0 siblings, 0 replies; 15+ messages in thread
From: Michael Meissner @ 2021-06-09 5:32 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:ad7f8ef29a2d47d85d309af8766b953d66a0335c
commit ad7f8ef29a2d47d85d309af8766b953d66a0335c
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Jun 9 01:32:16 2021 -0400
Revert patch.
gcc/testsuite
2021-06-09 Michael Meissner <meissner@linux.ibm.com>
Revert patch.
PR testsuite/100168
* gcc.dg/pr56727-2.c: Add support for PC-relative calls.
Diff:
---
gcc/testsuite/gcc.dg/pr56727-2.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.dg/pr56727-2.c b/gcc/testsuite/gcc.dg/pr56727-2.c
index 77fdf4bc350..c54369ed25e 100644
--- a/gcc/testsuite/gcc.dg/pr56727-2.c
+++ b/gcc/testsuite/gcc.dg/pr56727-2.c
@@ -18,4 +18,4 @@ void h ()
/* { dg-final { scan-assembler "@(PLT|plt)" { target i?86-*-* x86_64-*-* } } } */
/* { dg-final { scan-assembler "@(PLT|plt)" { target { powerpc*-*-linux* && ilp32 } } } } */
-/* { dg-final { scan-assembler "(bl f\n\\s*nop)|(bl f@notoc)" { target { powerpc*-*-linux* && lp64 } } } } */
+/* { dg-final { scan-assembler "bl f\n\\s*nop" { target { powerpc*-*-linux* && lp64 } } } } */
^ permalink raw reply [flat|nested] 15+ messages in thread
* [gcc(refs/users/meissner/heads/work055)] Revert patch.
@ 2021-06-09 5:28 Michael Meissner
0 siblings, 0 replies; 15+ messages in thread
From: Michael Meissner @ 2021-06-09 5:28 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:1a1371c7ae1836999a8fbb5ff5b46382e7a3675c
commit 1a1371c7ae1836999a8fbb5ff5b46382e7a3675c
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Jun 9 01:26:17 2021 -0400
Revert patch.
gcc/testsuite/
2021-06-09 Michael Meissner <meissner@linux.ibm.com>
Revert patch.
PR testsuite/100167
* gcc.target/powerpc/fold-vec-div-longlong.c:
* gcc.target/powerpc/fold-vec-mult-longlong.c: Fix expected code
generation on power10.
Diff:
---
gcc/testsuite/gcc.target/powerpc/fold-vec-div-longlong.c | 7 ++-----
gcc/testsuite/gcc.target/powerpc/fold-vec-mult-longlong.c | 3 +--
2 files changed, 3 insertions(+), 7 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-div-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-div-longlong.c
index 8a64814afa0..312e984d3cc 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-div-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-div-longlong.c
@@ -19,8 +19,5 @@ test6 (vector unsigned long long x, vector unsigned long long y)
{
return vec_div (x, y);
}
-
-/* { dg-final { scan-assembler-times {\mdivd\M} 2 { target { !has_arch_pwr10 } } } } */
-/* { dg-final { scan-assembler-times {\mdivdu\M} 2 { target { !has_arch_pwr10 } } } } */
-/* { dg-final { scan-assembler-times {\mvdivsd\M} 1 { target { has_arch_pwr10 } } } } */
-/* { dg-final { scan-assembler-times {\mvdivud\M} 1 { target { has_arch_pwr10 } } } } */
+/* { dg-final { scan-assembler-times {\mdivd\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mdivdu\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-longlong.c
index f18fbd0d09b..38dba9f5023 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-longlong.c
@@ -20,6 +20,5 @@ test6 (vector unsigned long long x, vector unsigned long long y)
return vec_mul (x, y);
}
-/* { dg-final { scan-assembler-times {\mmulld\M} 4 { target { lp64 && ! has_arch_pwr10 } } } } */
-/* { dg-final { scan-assembler-times {\mvmulld\M} 1 { target { has_arch_pwr10 } } } } */
+/* { dg-final { scan-assembler-times "\[ \t\]mulld " 4 { target lp64 } } } */
^ permalink raw reply [flat|nested] 15+ messages in thread
* [gcc(refs/users/meissner/heads/work055)] Revert patch.
@ 2021-06-08 4:10 Michael Meissner
0 siblings, 0 replies; 15+ messages in thread
From: Michael Meissner @ 2021-06-08 4:10 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:84f081332969ec50956570eecc8e5be98f6238d7
commit 84f081332969ec50956570eecc8e5be98f6238d7
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue Jun 8 00:10:27 2021 -0400
Revert patch.
gcc/
2021-06-08 Michael Meissner <meissner@linux.ibm.com>
Revert patch.
* config/rs6000/rs6000.c (rs6000_emit_minmax): Add support for ISA
3.1 IEEE 128-bit floating point xsmaxcqp and xsmincqp
instructions.
* config/rs6000/rs6000.md (s<minmax><mode>3, IEEE128 iterator):
New insns.
gcc/testsuite/
2021-06-08 Michael Meissner <meissner@linux.ibm.com>
Revert patch.
* gcc.target/powerpc/float128-minmax-2.c: New test.
* gcc.target/powerpc/float128-minmax.c: Adjust expected code for
power10.
* lib/target-supports.exp (check_effective_target_has_arch_pwr10):
New target support.
Diff:
---
gcc/config/rs6000/rs6000.c | 3 +--
gcc/config/rs6000/rs6000.md | 11 -----------
gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c | 15 ---------------
gcc/testsuite/gcc.target/powerpc/float128-minmax.c | 7 ++-----
gcc/testsuite/lib/target-supports.exp | 10 ----------
5 files changed, 3 insertions(+), 43 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 1651788df6a..b01bb5c8191 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -16103,8 +16103,7 @@ rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
/* VSX/altivec have direct min/max insns. */
if ((code == SMAX || code == SMIN)
&& (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)
- || (mode == SFmode && VECTOR_UNIT_VSX_P (DFmode))
- || (TARGET_POWER10 && TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode))))
+ || (mode == SFmode && VECTOR_UNIT_VSX_P (DFmode))))
{
emit_insn (gen_rtx_SET (dest, gen_rtx_fmt_ee (code, mode, op0, op1)));
return;
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 064c3a2d9d6..3f59b544f6a 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -5214,17 +5214,6 @@
}
[(set_attr "type" "fp")])
-;; Min/max for ISA 3.1 IEEE 128-bit floating point
-(define_insn "s<minmax><mode>3"
- [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
- (fp_minmax:IEEE128
- (match_operand:IEEE128 1 "altivec_register_operand" "v")
- (match_operand:IEEE128 2 "altivec_register_operand" "v")))]
- "TARGET_POWER10"
- "xs<minmax>cqp %0,%1,%2"
- [(set_attr "type" "vecfloat")
- (set_attr "size" "128")])
-
;; The conditional move instructions allow us to perform max and min operations
;; even when we don't have the appropriate max/min instruction using the FSEL
;; instruction.
diff --git a/gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c b/gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c
deleted file mode 100644
index c71ba08c9f8..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c
+++ /dev/null
@@ -1,15 +0,0 @@
-/* { dg-require-effective-target ppc_float128_hw } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -ffast-math" } */
-
-#ifndef TYPE
-#define TYPE _Float128
-#endif
-
-/* Test that the fminf128/fmaxf128 functions generate if/then/else and not a
- call. */
-TYPE f128_min (TYPE a, TYPE b) { return __builtin_fminf128 (a, b); }
-TYPE f128_max (TYPE a, TYPE b) { return __builtin_fmaxf128 (a, b); }
-
-/* { dg-final { scan-assembler {\mxsmaxcqp\M} } } */
-/* { dg-final { scan-assembler {\mxsmincqp\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/float128-minmax.c b/gcc/testsuite/gcc.target/powerpc/float128-minmax.c
index 9a5059e2d68..fe397518f2f 100644
--- a/gcc/testsuite/gcc.target/powerpc/float128-minmax.c
+++ b/gcc/testsuite/gcc.target/powerpc/float128-minmax.c
@@ -1,7 +1,7 @@
/* { dg-do compile { target lp64 } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-require-effective-target float128 } */
-/* { dg-options "-O2 -ffast-math" } */
+/* { dg-options "-mpower9-vector -O2 -ffast-math" } */
#ifndef TYPE
#define TYPE _Float128
@@ -12,8 +12,5 @@
TYPE f128_min (TYPE a, TYPE b) { return __builtin_fminf128 (a, b); }
TYPE f128_max (TYPE a, TYPE b) { return __builtin_fmaxf128 (a, b); }
-/* Note power10 has native min/max instructions. */
-/* { dg-final { scan-assembler {\mxscmpuqp\M} } { target { ! has_arch_pwr10 } } } */
-/* { dg-final { scan-assembler {\mxsmincqp\M} } { target { has_arch_pwr10 } } } */
-/* { dg-final { scan-assembler {\mxsmaxcqp\M} } { target { has_arch_pwr10 } } } */
+/* { dg-final { scan-assembler {\mxscmpuqp\M} } } */
/* { dg-final { scan-assembler-not {\mbl\M} } } */
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 789723fb287..7f78c5593ac 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -6127,16 +6127,6 @@ proc check_effective_target_has_arch_pwr9 { } {
}]
}
-proc check_effective_target_has_arch_pwr10 { } {
- return [check_no_compiler_messages arch_pwr10 assembly {
- #ifndef _ARCH_PWR10
- #error does not have power10 support.
- #else
- /* "has power10 support" */
- #endif
- }]
-}
-
# Return 1 if this is a PowerPC target supporting -mcpu=power10.
# Limit this to 64-bit linux systems for now until other targets support
# power10.
^ permalink raw reply [flat|nested] 15+ messages in thread
* [gcc(refs/users/meissner/heads/work055)] Revert patch.
@ 2021-06-08 3:46 Michael Meissner
0 siblings, 0 replies; 15+ messages in thread
From: Michael Meissner @ 2021-06-08 3:46 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:015a5cce454dba9c544658c0b89182b783d0339a
commit 015a5cce454dba9c544658c0b89182b783d0339a
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Mon Jun 7 23:46:02 2021 -0400
Revert patch.
gcc/
2021-06-07 Michael Meissner <meissner@linux.ibm.com>
Revert patch.
* config/rs6000/rs6000.c (rs6000_emit_minmax): Add support for ISA
3.1 IEEE 128-bit floating point xsmaxcqp and xsmincqp
instructions.
* config/rs6000/rs6000.md (s<minmax><mode>3, IEEE128 iterator):
New insns.
gcc/testsuite/
2021-06-07 Michael Meissner <meissner@linux.ibm.com>
Revert patch.
* gcc.target/powerpc/float128-minmax-2.c: New test.
* gcc.target/powerpc/float128-minmax.c: Adjust expected code for
power10.
* lib/target-supports.exp (check_effective_target_has_arch_pwr10):
New target support.
Diff:
---
gcc/config/rs6000/rs6000.c | 3 +--
gcc/config/rs6000/rs6000.md | 11 -----------
gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c | 15 ---------------
gcc/testsuite/gcc.target/powerpc/float128-minmax.c | 7 ++-----
gcc/testsuite/lib/target-supports.exp | 10 ----------
5 files changed, 3 insertions(+), 43 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 1651788df6a..b01bb5c8191 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -16103,8 +16103,7 @@ rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
/* VSX/altivec have direct min/max insns. */
if ((code == SMAX || code == SMIN)
&& (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)
- || (mode == SFmode && VECTOR_UNIT_VSX_P (DFmode))
- || (TARGET_POWER10 && TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode))))
+ || (mode == SFmode && VECTOR_UNIT_VSX_P (DFmode))))
{
emit_insn (gen_rtx_SET (dest, gen_rtx_fmt_ee (code, mode, op0, op1)));
return;
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 064c3a2d9d6..3f59b544f6a 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -5214,17 +5214,6 @@
}
[(set_attr "type" "fp")])
-;; Min/max for ISA 3.1 IEEE 128-bit floating point
-(define_insn "s<minmax><mode>3"
- [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
- (fp_minmax:IEEE128
- (match_operand:IEEE128 1 "altivec_register_operand" "v")
- (match_operand:IEEE128 2 "altivec_register_operand" "v")))]
- "TARGET_POWER10"
- "xs<minmax>cqp %0,%1,%2"
- [(set_attr "type" "vecfloat")
- (set_attr "size" "128")])
-
;; The conditional move instructions allow us to perform max and min operations
;; even when we don't have the appropriate max/min instruction using the FSEL
;; instruction.
diff --git a/gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c b/gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c
deleted file mode 100644
index c71ba08c9f8..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c
+++ /dev/null
@@ -1,15 +0,0 @@
-/* { dg-require-effective-target ppc_float128_hw } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -ffast-math" } */
-
-#ifndef TYPE
-#define TYPE _Float128
-#endif
-
-/* Test that the fminf128/fmaxf128 functions generate if/then/else and not a
- call. */
-TYPE f128_min (TYPE a, TYPE b) { return __builtin_fminf128 (a, b); }
-TYPE f128_max (TYPE a, TYPE b) { return __builtin_fmaxf128 (a, b); }
-
-/* { dg-final { scan-assembler {\mxsmaxcqp\M} } } */
-/* { dg-final { scan-assembler {\mxsmincqp\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/float128-minmax.c b/gcc/testsuite/gcc.target/powerpc/float128-minmax.c
index cdff6943bc3..fe397518f2f 100644
--- a/gcc/testsuite/gcc.target/powerpc/float128-minmax.c
+++ b/gcc/testsuite/gcc.target/powerpc/float128-minmax.c
@@ -1,7 +1,7 @@
/* { dg-do compile { target lp64 } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-require-effective-target float128 } */
-/* { dg-options "-O2 -ffast-math" } */
+/* { dg-options "-mpower9-vector -O2 -ffast-math" } */
#ifndef TYPE
#define TYPE _Float128
@@ -12,8 +12,5 @@
TYPE f128_min (TYPE a, TYPE b) { return __builtin_fminf128 (a, b); }
TYPE f128_max (TYPE a, TYPE b) { return __builtin_fmaxf128 (a, b); }
-/* Note power10 has native min/max instructions. */
-/* { dg-final { scan-assembler {\mxscmpuqp\M} } target { ! has_arch_pwr10 } } */
-/* { dg-final { scan-assembler {\mxsmincqp\M} } target { has_arch_pwr10 } } */
-/* { dg-final { scan-assembler {\mxsmaxcqp\M} } target { has_arch_pwr10 } } */
+/* { dg-final { scan-assembler {\mxscmpuqp\M} } } */
/* { dg-final { scan-assembler-not {\mbl\M} } } */
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 789723fb287..7f78c5593ac 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -6127,16 +6127,6 @@ proc check_effective_target_has_arch_pwr9 { } {
}]
}
-proc check_effective_target_has_arch_pwr10 { } {
- return [check_no_compiler_messages arch_pwr10 assembly {
- #ifndef _ARCH_PWR10
- #error does not have power10 support.
- #else
- /* "has power10 support" */
- #endif
- }]
-}
-
# Return 1 if this is a PowerPC target supporting -mcpu=power10.
# Limit this to 64-bit linux systems for now until other targets support
# power10.
^ permalink raw reply [flat|nested] 15+ messages in thread
* [gcc(refs/users/meissner/heads/work055)] Revert patch.
@ 2021-06-08 2:58 Michael Meissner
0 siblings, 0 replies; 15+ messages in thread
From: Michael Meissner @ 2021-06-08 2:58 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:bc4b76e491a481c25cb8803055fc213c87831070
commit bc4b76e491a481c25cb8803055fc213c87831070
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Mon Jun 7 22:58:08 2021 -0400
Revert patch.
gcc/
2021-06-07 Michael Meissner <meissner@linux.ibm.com>
Revert patch.
* config/rs6000/rs6000.c (rs6000_emit_minmax): Add support for ISA
3.1 IEEE 128-bit floating point xsmaxcqp and xsmincqp instructions.
* config/rs6000/rs6000.md (s<minmax><mode>3, IEEE128 iterator):
New insns.
gcc/testsuite/
2021-06-07 Michael Meissner <meissner@linux.ibm.com>
Revert patch.
* gcc.target/powerpc/float128-minmax-2.c: New test.
* gcc.target/powerpc/float128-minmax.c: Do not run on power10.
* lib/target-supports.exp (check_effective_target_has_arch_pwr10):
New target support.
Diff:
---
gcc/config/rs6000/rs6000.c | 3 +--
gcc/config/rs6000/rs6000.md | 11 -----------
gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c | 15 ---------------
gcc/testsuite/gcc.target/powerpc/float128-minmax.c | 7 ++-----
gcc/testsuite/lib/target-supports.exp | 10 ----------
5 files changed, 3 insertions(+), 43 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 1651788df6a..b01bb5c8191 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -16103,8 +16103,7 @@ rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
/* VSX/altivec have direct min/max insns. */
if ((code == SMAX || code == SMIN)
&& (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)
- || (mode == SFmode && VECTOR_UNIT_VSX_P (DFmode))
- || (TARGET_POWER10 && TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode))))
+ || (mode == SFmode && VECTOR_UNIT_VSX_P (DFmode))))
{
emit_insn (gen_rtx_SET (dest, gen_rtx_fmt_ee (code, mode, op0, op1)));
return;
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 064c3a2d9d6..3f59b544f6a 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -5214,17 +5214,6 @@
}
[(set_attr "type" "fp")])
-;; Min/max for ISA 3.1 IEEE 128-bit floating point
-(define_insn "s<minmax><mode>3"
- [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
- (fp_minmax:IEEE128
- (match_operand:IEEE128 1 "altivec_register_operand" "v")
- (match_operand:IEEE128 2 "altivec_register_operand" "v")))]
- "TARGET_POWER10"
- "xs<minmax>cqp %0,%1,%2"
- [(set_attr "type" "vecfloat")
- (set_attr "size" "128")])
-
;; The conditional move instructions allow us to perform max and min operations
;; even when we don't have the appropriate max/min instruction using the FSEL
;; instruction.
diff --git a/gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c b/gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c
deleted file mode 100644
index c71ba08c9f8..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c
+++ /dev/null
@@ -1,15 +0,0 @@
-/* { dg-require-effective-target ppc_float128_hw } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -ffast-math" } */
-
-#ifndef TYPE
-#define TYPE _Float128
-#endif
-
-/* Test that the fminf128/fmaxf128 functions generate if/then/else and not a
- call. */
-TYPE f128_min (TYPE a, TYPE b) { return __builtin_fminf128 (a, b); }
-TYPE f128_max (TYPE a, TYPE b) { return __builtin_fmaxf128 (a, b); }
-
-/* { dg-final { scan-assembler {\mxsmaxcqp\M} } } */
-/* { dg-final { scan-assembler {\mxsmincqp\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/float128-minmax.c b/gcc/testsuite/gcc.target/powerpc/float128-minmax.c
index 76bb88b170d..fe397518f2f 100644
--- a/gcc/testsuite/gcc.target/powerpc/float128-minmax.c
+++ b/gcc/testsuite/gcc.target/powerpc/float128-minmax.c
@@ -1,10 +1,7 @@
/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p9vector_ok && ! has_arch_pwr10 } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-require-effective-target float128 } */
-/* { dg-options "-O2 -ffast-math" } */
-
-/* We don't run this test on power10 because power10 has instructions to
- implement min/max directly. */
+/* { dg-options "-mpower9-vector -O2 -ffast-math" } */
#ifndef TYPE
#define TYPE _Float128
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 789723fb287..7f78c5593ac 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -6127,16 +6127,6 @@ proc check_effective_target_has_arch_pwr9 { } {
}]
}
-proc check_effective_target_has_arch_pwr10 { } {
- return [check_no_compiler_messages arch_pwr10 assembly {
- #ifndef _ARCH_PWR10
- #error does not have power10 support.
- #else
- /* "has power10 support" */
- #endif
- }]
-}
-
# Return 1 if this is a PowerPC target supporting -mcpu=power10.
# Limit this to 64-bit linux systems for now until other targets support
# power10.
^ permalink raw reply [flat|nested] 15+ messages in thread
* [gcc(refs/users/meissner/heads/work055)] Revert patch.
@ 2021-06-08 1:04 Michael Meissner
0 siblings, 0 replies; 15+ messages in thread
From: Michael Meissner @ 2021-06-08 1:04 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:e1c1b4418ccb74859339609b423ef6d073d81b06
commit e1c1b4418ccb74859339609b423ef6d073d81b06
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Mon Jun 7 21:03:30 2021 -0400
Revert patch.
gcc/
2021-06-07 Michael Meissner <meissner@linux.ibm.com>
Revert patch
* config/rs6000/rs6000.c (rs6000_emit_minmax): Add support for ISA
3.1 IEEE 128-bit floating point xsmaxcqp and xsmincqp instructions.
* config/rs6000/rs6000.md (s<minmax><mode>3, IEEE128 iterator):
New insns.
gcc/testsuite/
2021-06-07 Michael Meissner <meissner@linux.ibm.com>
Revert patch
* gcc.target/powerpc/float128-minmax-2.c: New test.
* gcc.target/powerpc/float128-minmax.c: Do not run on power10.
Diff:
---
gcc/config/rs6000/rs6000.c | 3 +--
gcc/config/rs6000/rs6000.md | 11 -----------
gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c | 15 ---------------
gcc/testsuite/gcc.target/powerpc/float128-minmax.c | 6 ++----
4 files changed, 3 insertions(+), 32 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 1651788df6a..b01bb5c8191 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -16103,8 +16103,7 @@ rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
/* VSX/altivec have direct min/max insns. */
if ((code == SMAX || code == SMIN)
&& (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)
- || (mode == SFmode && VECTOR_UNIT_VSX_P (DFmode))
- || (TARGET_POWER10 && TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode))))
+ || (mode == SFmode && VECTOR_UNIT_VSX_P (DFmode))))
{
emit_insn (gen_rtx_SET (dest, gen_rtx_fmt_ee (code, mode, op0, op1)));
return;
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 064c3a2d9d6..3f59b544f6a 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -5214,17 +5214,6 @@
}
[(set_attr "type" "fp")])
-;; Min/max for ISA 3.1 IEEE 128-bit floating point
-(define_insn "s<minmax><mode>3"
- [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
- (fp_minmax:IEEE128
- (match_operand:IEEE128 1 "altivec_register_operand" "v")
- (match_operand:IEEE128 2 "altivec_register_operand" "v")))]
- "TARGET_POWER10"
- "xs<minmax>cqp %0,%1,%2"
- [(set_attr "type" "vecfloat")
- (set_attr "size" "128")])
-
;; The conditional move instructions allow us to perform max and min operations
;; even when we don't have the appropriate max/min instruction using the FSEL
;; instruction.
diff --git a/gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c b/gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c
deleted file mode 100644
index c71ba08c9f8..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c
+++ /dev/null
@@ -1,15 +0,0 @@
-/* { dg-require-effective-target ppc_float128_hw } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -ffast-math" } */
-
-#ifndef TYPE
-#define TYPE _Float128
-#endif
-
-/* Test that the fminf128/fmaxf128 functions generate if/then/else and not a
- call. */
-TYPE f128_min (TYPE a, TYPE b) { return __builtin_fminf128 (a, b); }
-TYPE f128_max (TYPE a, TYPE b) { return __builtin_fmaxf128 (a, b); }
-
-/* { dg-final { scan-assembler {\mxsmaxcqp\M} } } */
-/* { dg-final { scan-assembler {\mxsmincqp\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/float128-minmax.c b/gcc/testsuite/gcc.target/powerpc/float128-minmax.c
index d7bc60af9d8..fe397518f2f 100644
--- a/gcc/testsuite/gcc.target/powerpc/float128-minmax.c
+++ b/gcc/testsuite/gcc.target/powerpc/float128-minmax.c
@@ -1,10 +1,8 @@
/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p9vector_ok && ! power10_hw } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-require-effective-target float128 } */
-/* { dg-options "-O2 -ffast-math" } */
+/* { dg-options "-mpower9-vector -O2 -ffast-math" } */
-/* We don't run this test on power10 because power10 has instructions to
- implement min/max directly. */
#ifndef TYPE
#define TYPE _Float128
#endif
^ permalink raw reply [flat|nested] 15+ messages in thread
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