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* [gcc(refs/users/meissner/heads/work062)] Do not allow prefixed loads/stores in PowerPC asm.
@ 2021-07-31 3:56 Michael Meissner
0 siblings, 0 replies; 4+ messages in thread
From: Michael Meissner @ 2021-07-31 3:56 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:3eeb65a6c5a45afa88441c998f107fe3f9772f2c
commit 3eeb65a6c5a45afa88441c998f107fe3f9772f2c
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Jul 30 23:55:40 2021 -0400
Do not allow prefixed loads/stores in PowerPC asm.
The PowerPC has noraml loads and stores and then it has prefixed loads and
stores. The prefixed loads and stores have different names and format
than the normal loads and stores. This patch adds a new hook that is run
in the passes before reload to ensure that no prefixed memory is generated
by optimizations.
This patch contains the PowerPC bits to ensure that prefixed addresses are
not passed as asm operands.
2021-07-31 Michael Meissner <meissner@linux.ibm.com>
gcc/
PR target/98519
* config/rs6000/rs6000.c (rs6000_asm_operand_p): New function.
(TARGET_MD_ASM_OPERAND_P): Override md_asm_operand_p hook.
gcc/testsuite/
PR target/98519
* gcc.target/powerpc/pr98519.c: New test.
Diff:
---
gcc/config/rs6000/rs6000.c | 28 ++++++++++++++++++++++++++++
gcc/doc/tm.texi.in | 2 ++
gcc/testsuite/gcc.target/powerpc/pr98519.c | 20 ++++++++++++++++++++
3 files changed, 50 insertions(+)
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 2de5a96e1b6..73e87c3cbc6 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -1196,6 +1196,8 @@ static bool rs6000_secondary_reload_move (enum rs6000_reg_type,
bool);
rtl_opt_pass *make_pass_analyze_swaps (gcc::context*);
+static bool rs6000_asm_operand_p (rtx, const char *, const char **);
+
/* Hash table stuff for keeping track of TOC entries. */
struct GTY((for_user)) toc_hash_struct
@@ -1639,6 +1641,9 @@ static const struct attribute_spec rs6000_attribute_table[] =
#undef TARGET_LEGITIMATE_ADDRESS_P
#define TARGET_LEGITIMATE_ADDRESS_P rs6000_legitimate_address_p
+#undef TARGET_MD_ASM_OPERAND_P
+#define TARGET_MD_ASM_OPERAND_P rs6000_asm_operand_p
+
#undef TARGET_MODE_DEPENDENT_ADDRESS_P
#define TARGET_MODE_DEPENDENT_ADDRESS_P rs6000_mode_dependent_address_p
@@ -9921,6 +9926,29 @@ rs6000_offsettable_memref_p (rtx op, machine_mode reg_mode, bool strict)
strict, worst_case);
}
+/* Add additional constraints for asm operands. We use it to prevent
+ prefixed loads/stores from appearing in normal asm statements.
+
+ At the moment, we just ban all prefixed loads/stores. If we add a
+ constraint specifically for prefixed loads/stores, we might need to scan the
+ constraint string for that constraint. */
+
+static bool
+rs6000_asm_operand_p (rtx op,
+ const char *constraint ATTRIBUTE_UNUSED,
+ const char **constraints ATTRIBUTE_UNUSED)
+{
+ if (TARGET_PREFIXED && MEM_P (op))
+ {
+ rtx addr = XEXP (op, 0);
+ machine_mode mode = GET_MODE (op);
+ if (address_is_prefixed (addr, mode, NON_PREFIXED_DEFAULT))
+ return false;
+ }
+
+ return true;
+}
+
/* Determine the reassociation width to be used in reassociate_bb.
This takes into account how many parallel operations we
can actually do of a given type, and also the latency.
diff --git a/gcc/doc/tm.texi.in b/gcc/doc/tm.texi.in
index 4a522ae7e2e..21e013fa274 100644
--- a/gcc/doc/tm.texi.in
+++ b/gcc/doc/tm.texi.in
@@ -4066,6 +4066,8 @@ accept.
@hook TARGET_LEGITIMATE_ADDRESS_P
+@hook TARGET_MD_ASM_OPERAND_P
+
@defmac TARGET_MEM_CONSTRAINT
A single character to be used instead of the default @code{'m'}
character for general memory addresses. This defines the constraint
diff --git a/gcc/testsuite/gcc.target/powerpc/pr98519.c b/gcc/testsuite/gcc.target/powerpc/pr98519.c
new file mode 100644
index 00000000000..25918bac3ed
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr98519.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
+
+/* Compile with -mcpu=power10. The lxsd instruction should not be replaced
+ with a plxsd. */
+typedef vector double vf64_t;
+
+static double test_f64[16];
+
+vf64_t
+bug (void)
+{
+ vf64_t j0;
+ __asm__("lxsd%X1 %0,%1;" : "=v" (j0) : "m" (test_f64));
+ return j0;
+}
+
+/* { dg-final { scan-assembler {\mlxsd\M} } } */
+/* { dg-final { scan-assembler-not {\mplxsd\M} } } */
^ permalink raw reply [flat|nested] 4+ messages in thread
* [gcc(refs/users/meissner/heads/work062)] Do not allow prefixed loads/stores in PowerPC asm.
@ 2021-08-02 4:09 Michael Meissner
0 siblings, 0 replies; 4+ messages in thread
From: Michael Meissner @ 2021-08-02 4:09 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:0827cca67bc59441d519a6fb2bb43e137ce0dbbc
commit 0827cca67bc59441d519a6fb2bb43e137ce0dbbc
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Mon Aug 2 00:08:37 2021 -0400
Do not allow prefixed loads/stores in PowerPC asm.
The PowerPC has noraml loads and stores and then it has prefixed loads and
stores. The prefixed loads and stores have different names and format
than the normal loads and stores. The patch changes the 'm' constraint
from returning true for all valid memory insns to return true for all
valid non-prefixed memory insns. This allows __asm__ code to continue to
use the "m" constraint without getting assembler errors due to the non
prefixed instruction was being used.
I use the constraint "k" (which was unused) to be a replacement for the
"m" constraint. All of the mov insns and extend insns from memory were
changed to use the "k" constraint instead of the "m" constraint.
2021-08-02 Michael Meissner <meissner@linux.ibm.com>
gcc/
PR target/98519
* config/rs6000/constraints.md (top level): Adjust comment about
the available unused constraints.
(constraint "m"). New constraint.
* config/rs6000/mma.h (movoo): Use "k" instead of "m".
(movxo): Likewise.
(vsx_assemble_pair): Likewise.
(vsx_disassemble_pair): Likewise.
(mma_assemble_acc): Likewise.
(mma_disassemble_acc): Likewise.
* config/rs6000/rs6000.h (TARGET_MEM_CONSTRAINT): Define, making
'k' the new memory cosntraint.
* config/rs6000/rs6000.md (ptrm): Use "k" instead of "m".
(zero_extendqi<mode>2): Likewise.
(zero_extendhi<mode>2): Likewise.
(zero_extendsi<mode>2): Likewise.
(extendhi<mode>2): Likewise.
(signbit<mode>2_dm_mem): Likewise.
(floatdidf2_mem): Likewise.
(floatunsdidf2_mem): Likewise.
(floatdisf2_mem): Likewise.
(floatunsdisf2_mem): Likewise.
(movsi_internal1): Likewise.
(movdi_from_sf_zero_ext): Likewise.
(mov<mode>_internal, QHI iterator): Likewise.
(movsf_hardfloat): Likewise.
(movsd_hardfloat): Likewise.
(mov<mode>_softfloat): Likewise.
(mov<mode>_hardfloat32): Likewise.
(mov<mode>_hardfloat64): Likewise.
(mov<mode>_64bit_dm): Likewise.
(movtd_64bit_nodm): Likewise.
(mov<mode>_32bit. FMOVE128 iterator): Likewise.
(extenddf<mode>2, IBM128 iterator): Likewise.
(extendtf<mode>2): Likewise.
(reload_<mode>_load): Likewise.
(reload_<RELOAD:mode>_<P:mptrsize>_load): Likewise.
(movdi_internal32): Likewise.
(movdi_internal64): Likewise.
(pltseq_tocsave_<mode>): Likewise.
(probe_stack_<mode>): Likewise.
(stack_protect_setsi): Likewise.
(stack_protect_testsi): Likewise.
(crsave): Likewise.
(stmw): Likewise.
(save_gpregs_<mode>_r11): Likewise.
(save_gpregs_<mode>_r12): Likewise.
(save_gpregs_<mode>_r1): Likewise.
(save_fpregs_<mode>_r11): Likewise.
(save_fpregs_<mode>_r12): Likewise.
(save_fpregs_<mode>_r1): Likewise.
(mtcrfsi): Likewise.
(restore_gpregs_<mode>_r11): Likewise.
(restore_gpregs_<mode>_r12): Likewise.
(restore_gpregs_<mode>_r1): Likewise.
(return_and_restore_gpregs): Likewise.
(return_and_restore_fpregs): Likewise.
(hashst): Likewise.
(hashchk): Likewise.
gcc/testsuite/
PR target/98519
* gcc.target/powerpc/pr98519.c: New test.
Diff:
---
gcc/config/rs6000/constraints.md | 10 +-
gcc/config/rs6000/mma.md | 24 ++---
gcc/config/rs6000/rs6000.h | 7 ++
gcc/config/rs6000/rs6000.md | 148 ++++++++++++++---------------
gcc/testsuite/gcc.target/powerpc/pr98519.c | 20 ++++
5 files changed, 122 insertions(+), 87 deletions(-)
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index 561ce9797af..a0a3cdb33a8 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -17,7 +17,7 @@
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
-;; Available constraint letters: e k q t u A B C D S T
+;; Available constraint letters: q t u A B C D S T
;; Register constraints
@@ -65,6 +65,14 @@
(define_register_constraint "l" "LINK_REGS"
"The link register, @code{lr}.")
+; This defines 'm' as normal memory constraint. This is only possible
+; since the standard memory constraint is re-defined in rs6000.h using
+; the TARGET_MEM_CONSTRAINT macro (to be k).
+(define_memory_constraint "m"
+ "Matches the most general non-prefixed memory address, suitable for asm."
+ (and (match_code "mem")
+ (not (match_operand 0 "prefixed_memory"))))
+
(define_register_constraint "x" "CR0_REGS"
"Condition register field 0, @code{cr0}.")
diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md
index 1f6fc03d2ac..f04adee4c1b 100644
--- a/gcc/config/rs6000/mma.md
+++ b/gcc/config/rs6000/mma.md
@@ -271,8 +271,8 @@
})
(define_insn_and_split "*movoo"
- [(set (match_operand:OO 0 "nonimmediate_operand" "=wa,m,wa")
- (match_operand:OO 1 "input_operand" "m,wa,wa"))]
+ [(set (match_operand:OO 0 "nonimmediate_operand" "=wa,k,wa")
+ (match_operand:OO 1 "input_operand" "k,wa,wa"))]
"TARGET_MMA
&& (gpc_reg_operand (operands[0], OOmode)
|| gpc_reg_operand (operands[1], OOmode))"
@@ -303,8 +303,8 @@
})
(define_insn_and_split "*movxo"
- [(set (match_operand:XO 0 "nonimmediate_operand" "=d,m,d")
- (match_operand:XO 1 "input_operand" "m,d,d"))]
+ [(set (match_operand:XO 0 "nonimmediate_operand" "=d,k,d")
+ (match_operand:XO 1 "input_operand" "k,d,d"))]
"TARGET_MMA
&& (gpc_reg_operand (operands[0], XOmode)
|| gpc_reg_operand (operands[1], XOmode))"
@@ -337,8 +337,8 @@
(define_insn_and_split "*vsx_assemble_pair"
[(set (match_operand:OO 0 "vsx_register_operand" "=wa")
- (unspec:OO [(match_operand:V16QI 1 "mma_assemble_input_operand" "mwa")
- (match_operand:V16QI 2 "mma_assemble_input_operand" "mwa")]
+ (unspec:OO [(match_operand:V16QI 1 "mma_assemble_input_operand" "kwa")
+ (match_operand:V16QI 2 "mma_assemble_input_operand" "kwa")]
UNSPEC_MMA_ASSEMBLE))]
"TARGET_MMA"
"#"
@@ -368,7 +368,7 @@
})
(define_insn_and_split "*vsx_disassemble_pair"
- [(set (match_operand:V16QI 0 "mma_disassemble_output_operand" "=mwa")
+ [(set (match_operand:V16QI 0 "mma_disassemble_output_operand" "=kwa")
(unspec:V16QI [(match_operand:OO 1 "vsx_register_operand" "wa")
(match_operand 2 "const_0_to_1_operand")]
UNSPEC_MMA_EXTRACT))]
@@ -403,10 +403,10 @@
(define_insn_and_split "*mma_assemble_acc"
[(set (match_operand:XO 0 "fpr_reg_operand" "=d")
- (unspec:XO [(match_operand:V16QI 1 "mma_assemble_input_operand" "mwa")
- (match_operand:V16QI 2 "mma_assemble_input_operand" "mwa")
- (match_operand:V16QI 3 "mma_assemble_input_operand" "mwa")
- (match_operand:V16QI 4 "mma_assemble_input_operand" "mwa")]
+ (unspec:XO [(match_operand:V16QI 1 "mma_assemble_input_operand" "kwa")
+ (match_operand:V16QI 2 "mma_assemble_input_operand" "kwa")
+ (match_operand:V16QI 3 "mma_assemble_input_operand" "kwa")
+ (match_operand:V16QI 4 "mma_assemble_input_operand" "kwa")]
UNSPEC_MMA_ASSEMBLE))]
"TARGET_MMA
&& fpr_reg_operand (operands[0], XOmode)"
@@ -438,7 +438,7 @@
})
(define_insn_and_split "*mma_disassemble_acc"
- [(set (match_operand:V16QI 0 "mma_disassemble_output_operand" "=mwa")
+ [(set (match_operand:V16QI 0 "mma_disassemble_output_operand" "=kwa")
(unspec:V16QI [(match_operand:XO 1 "fpr_reg_operand" "d")
(match_operand 2 "const_0_to_3_operand")]
UNSPEC_MMA_EXTRACT))]
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 4ca6372435d..14b99fb0edb 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -1248,6 +1248,13 @@ enum r6000_reg_class_enum {
extern enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX];
+/* This definition replaces the formerly used 'm' constraint with a
+ different constraint letter in order to avoid changing semantics of
+ the 'm' constraint when accepting new address formats in
+ TARGET_LEGITIMATE_ADDRESS_P. The constraint letter defined here
+ must not be used in insn definitions or inline assemblies. */
+#define TARGET_MEM_CONSTRAINT 'k'
+
/* The class value for index registers, and the one for base regs. */
#define INDEX_REG_CLASS GENERAL_REGS
#define BASE_REG_CLASS BASE_REGS
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index a84438f8545..38f235bbc2c 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -728,7 +728,7 @@
(define_mode_attr ptrload [(SI "lwz")
(DI "ld")])
-(define_mode_attr ptrm [(SI "m")
+(define_mode_attr ptrm [(SI "k")
(DI "Y")])
(define_mode_attr rreg [(SF "f")
@@ -836,7 +836,7 @@
(define_insn "zero_extendqi<mode>2"
[(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,r,^wa,^v")
- (zero_extend:EXTQI (match_operand:QI 1 "reg_or_mem_operand" "m,r,Z,v")))]
+ (zero_extend:EXTQI (match_operand:QI 1 "reg_or_mem_operand" "k,r,Z,v")))]
""
"@
lbz%U1%X1 %0,%1
@@ -890,7 +890,7 @@
(define_insn "zero_extendhi<mode>2"
[(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r,^wa,^v")
- (zero_extend:EXTHI (match_operand:HI 1 "reg_or_mem_operand" "m,r,Z,v")))]
+ (zero_extend:EXTHI (match_operand:HI 1 "reg_or_mem_operand" "k,r,Z,v")))]
""
"@
lhz%U1%X1 %0,%1
@@ -944,7 +944,7 @@
(define_insn "zero_extendsi<mode>2"
[(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r,d,wa,wa,r,wa")
- (zero_extend:EXTSI (match_operand:SI 1 "reg_or_mem_operand" "m,r,Z,Z,r,wa,wa")))]
+ (zero_extend:EXTSI (match_operand:SI 1 "reg_or_mem_operand" "k,r,Z,Z,r,wa,wa")))]
""
"@
lwz%U1%X1 %0,%1
@@ -1059,7 +1059,7 @@
(define_insn "*extendhi<mode>2"
[(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r,?*v,?*v")
- (sign_extend:EXTHI (match_operand:HI 1 "reg_or_mem_operand" "m,r,Z,v")))]
+ (sign_extend:EXTHI (match_operand:HI 1 "reg_or_mem_operand" "k,r,Z,v")))]
""
"@
lha%U1%X1 %0,%1
@@ -5140,7 +5140,7 @@
;; little endian, we have to load the 2nd double-word to get the sign bit.
(define_insn_and_split "*signbit<mode>2_dm_mem"
[(set (match_operand:DI 0 "gpc_reg_operand" "=b")
- (unspec:DI [(match_operand:SIGNBIT 1 "memory_operand" "m")]
+ (unspec:DI [(match_operand:SIGNBIT 1 "memory_operand" "k")]
UNSPEC_SIGNBIT))]
"TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
"#"
@@ -6656,7 +6656,7 @@
(define_insn_and_split "*floatdidf2_mem"
[(set (match_operand:DF 0 "gpc_reg_operand" "=d,wa")
- (float:DF (match_operand:DI 1 "memory_operand" "m,Z")))
+ (float:DF (match_operand:DI 1 "memory_operand" "k,Z")))
(clobber (match_scratch:DI 2 "=d,wa"))]
"TARGET_HARD_FLOAT && TARGET_FCFID"
"#"
@@ -6685,7 +6685,7 @@
(define_insn_and_split "*floatunsdidf2_mem"
[(set (match_operand:DF 0 "gpc_reg_operand" "=d,wa")
- (unsigned_float:DF (match_operand:DI 1 "memory_operand" "m,Z")))
+ (unsigned_float:DF (match_operand:DI 1 "memory_operand" "k,Z")))
(clobber (match_scratch:DI 2 "=d,wa"))]
"TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))"
"#"
@@ -6729,7 +6729,7 @@
(define_insn_and_split "*floatdisf2_mem"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f,wa,wa")
- (float:SF (match_operand:DI 1 "memory_operand" "m,m,Z")))
+ (float:SF (match_operand:DI 1 "memory_operand" "k,k,Z")))
(clobber (match_scratch:DI 2 "=d,d,wa"))]
"TARGET_HARD_FLOAT && TARGET_FCFIDS"
"#"
@@ -6810,7 +6810,7 @@
(define_insn_and_split "*floatunsdisf2_mem"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f,wa,wa")
- (unsigned_float:SF (match_operand:DI 1 "memory_operand" "m,m,Z")))
+ (unsigned_float:SF (match_operand:DI 1 "memory_operand" "k,k,Z")))
(clobber (match_scratch:DI 2 "=d,d,wa"))]
"TARGET_HARD_FLOAT && TARGET_FCFIDUS"
"#"
@@ -7297,7 +7297,7 @@
[(set (match_operand:SI 0 "nonimmediate_operand"
"=r, r,
r, d, v,
- m, Z, Z,
+ k, Z, Z,
r, r, r, r,
wa, wa, wa, v,
wa, v, v,
@@ -7305,7 +7305,7 @@
r, *h, *h")
(match_operand:SI 1 "input_operand"
"r, U,
- m, Z, Z,
+ k, Z, Z,
r, d, v,
I, L, eI, n,
wa, O, wM, wB,
@@ -7388,11 +7388,11 @@
(define_insn_and_split "movsi_from_sf"
[(set (match_operand:SI 0 "nonimmediate_operand"
- "=r, r, ?*d, ?*v, m,
- m, wY, Z, r, ?*wa,
+ "=r, r, ?*d, ?*v, k,
+ k, wY, Z, r, ?*wa,
wa")
(unspec:SI [(match_operand:SF 1 "input_operand"
- "r, m, Z, Z, r,
+ "r, k, Z, Z, r,
f, v, wa, wa, wa,
r")]
UNSPEC_SI_FROM_SF))
@@ -7454,7 +7454,7 @@
?v, wa")
(zero_extend:DI
(unspec:SI [(match_operand:SF 1 "input_operand"
- "r, m, Z, Z, wa,
+ "r, k, Z, Z, wa,
wa, r")]
UNSPEC_SI_FROM_SF)))
(clobber (match_scratch:V4SF 2
@@ -7586,11 +7586,11 @@
;; MTVSRWZ MF%1 MT%1 NOP
(define_insn "*mov<mode>_internal"
[(set (match_operand:QHI 0 "nonimmediate_operand"
- "=r, r, wa, m, Z, r,
+ "=r, r, wa, k, Z, r,
wa, wa, wa, v, ?v, r,
wa, r, *c*l, *h")
(match_operand:QHI 1 "input_operand"
- "r, m, Z, r, wa, i,
+ "r, k, Z, r, wa, i,
wa, O, wM, wB, wS, wa,
r, *h, r, 0"))]
"gpc_reg_operand (operands[0], <MODE>mode)
@@ -7727,11 +7727,11 @@
(define_insn "movsf_hardfloat"
[(set (match_operand:SF 0 "nonimmediate_operand"
- "=!r, f, v, wa, m, wY,
- Z, m, wa, !r, f, wa,
+ "=!r, f, v, wa, k, wY,
+ Z, k, wa, !r, f, wa,
!r, *c*l, !r, *h")
(match_operand:SF 1 "input_operand"
- "m, m, wY, Z, f, v,
+ "k, k, wY, Z, f, v,
wa, r, j, j, f, wa,
r, r, *h, 0"))]
"(register_operand (operands[0], SFmode)
@@ -7769,10 +7769,10 @@
;; FMR MR MT%0 MF%1 NOP
(define_insn "movsd_hardfloat"
[(set (match_operand:SD 0 "nonimmediate_operand"
- "=!r, d, m, Z, ?d, ?r,
+ "=!r, d, k, Z, ?d, ?r,
f, !r, *c*l, !r, *h")
(match_operand:SD 1 "input_operand"
- "m, Z, r, wx, r, d,
+ "k, Z, r, wx, r, d,
f, r, r, *h, 0"))]
"(register_operand (operands[0], SDmode)
|| register_operand (operands[1], SDmode))
@@ -7800,11 +7800,11 @@
;; LIS G-const. F/n-const NOP
(define_insn "*mov<mode>_softfloat"
[(set (match_operand:FMOVE32 0 "nonimmediate_operand"
- "=r, *c*l, r, r, m, r,
+ "=r, *c*l, r, r, k, r,
r, r, r, *h")
(match_operand:FMOVE32 1 "input_operand"
- "r, r, *h, m, r, I,
+ "r, r, *h, k, r, I,
L, G, Fn, 0"))]
"(gpc_reg_operand (operands[0], <MODE>mode)
@@ -7848,10 +7848,10 @@
;; STXSIWX GPR->VSX VSX->GPR GPR->GPR
(define_insn_and_split "movsf_from_si"
[(set (match_operand:SF 0 "nonimmediate_operand"
- "=!r, f, v, wa, m, Z,
+ "=!r, f, v, wa, k, Z,
Z, wa, ?r, !r")
(unspec:SF [(match_operand:SI 1 "input_operand"
- "m, m, wY, Z, r, f,
+ "k, k, wY, Z, r, f,
wa, r, wa, r")]
UNSPEC_SF_FROM_SI))
(clobber (match_scratch:DI 2
@@ -8028,11 +8028,11 @@
(define_insn "*mov<mode>_hardfloat32"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
- "=m, d, d, <f64_p9>, wY,
+ "=k, d, d, <f64_p9>, wY,
<f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
Y, r, !r")
(match_operand:FMOVE64 1 "input_operand"
- "d, m, d, wY, <f64_p9>,
+ "d, k, d, wY, <f64_p9>,
Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>,
r, Y, r"))]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT
@@ -8095,12 +8095,12 @@
(define_insn "*mov<mode>_hardfloat64"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
- "=m, d, d, <f64_p9>, wY,
+ "=k, d, d, <f64_p9>, wY,
<f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
YZ, r, !r, *c*l, !r,
*h, r, <f64_dm>")
(match_operand:FMOVE64 1 "input_operand"
- "d, m, d, wY, <f64_p9>,
+ "d, k, d, wY, <f64_p9>,
Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>,
r, YZ, r, r, *h,
0, <f64_dm>, r"))]
@@ -8193,11 +8193,11 @@
(define_insn_and_split "*mov<mode>_64bit_dm"
[(set (match_operand:FMOVE128_FPR 0 "nonimmediate_operand"
- "=m, d, d, d, Y,
+ "=k, d, d, d, Y,
r, r, r, r, d")
(match_operand:FMOVE128_FPR 1 "input_operand"
- "d, m, d, <zero_fp>, r,
+ "d, k, d, <zero_fp>, r,
<zero_fp>, Y, r, d, r"))]
"TARGET_HARD_FLOAT && TARGET_POWERPC64 && FLOAT128_2REG_P (<MODE>mode)
@@ -8217,8 +8217,8 @@
(set_attr "num_insns" "2")])
(define_insn_and_split "*movtd_64bit_nodm"
- [(set (match_operand:TD 0 "nonimmediate_operand" "=m,d,d,Y,r,r")
- (match_operand:TD 1 "input_operand" "d,m,d,r,Y,r"))]
+ [(set (match_operand:TD 0 "nonimmediate_operand" "=k,d,d,Y,r,r")
+ (match_operand:TD 1 "input_operand" "d,k,d,r,Y,r"))]
"TARGET_HARD_FLOAT && TARGET_POWERPC64 && !WORDS_BIG_ENDIAN
&& (gpc_reg_operand (operands[0], TDmode)
|| gpc_reg_operand (operands[1], TDmode))"
@@ -8234,8 +8234,8 @@
(set_attr "num_insns" "2,2,2,3,3,2")])
(define_insn_and_split "*mov<mode>_32bit"
- [(set (match_operand:FMOVE128_FPR 0 "nonimmediate_operand" "=m,d,d,d,Y,r,r")
- (match_operand:FMOVE128_FPR 1 "input_operand" "d,m,d,<zero_fp>,r,<zero_fp>Y,r"))]
+ [(set (match_operand:FMOVE128_FPR 0 "nonimmediate_operand" "=k,d,d,d,Y,r,r")
+ (match_operand:FMOVE128_FPR 1 "input_operand" "d,k,d,<zero_fp>,r,<zero_fp>Y,r"))]
"TARGET_HARD_FLOAT && !TARGET_POWERPC64
&& (FLOAT128_2REG_P (<MODE>mode)
|| int_reg_operand_not_pseudo (operands[0], <MODE>mode)
@@ -8303,7 +8303,7 @@
[(set (match_operand:IBM128 0 "gpc_reg_operand" "=d,d,&d")
(float_extend:IBM128
(match_operand:DF 1 "nonimmediate_operand" "d,m,d")))
- (use (match_operand:DF 2 "nonimmediate_operand" "m,m,d"))]
+ (use (match_operand:DF 2 "nonimmediate_operand" "k,k,d"))]
"!TARGET_VSX && TARGET_HARD_FLOAT
&& TARGET_LONG_DOUBLE_128 && FLOAT128_IBM_P (<MODE>mode)"
"#"
@@ -8882,7 +8882,7 @@
;; Reload patterns to support gpr load/store with misaligned mem.
;; and multiple gpr load/store at offset >= 0xfffc
(define_expand "reload_<mode>_store"
- [(parallel [(match_operand 0 "memory_operand" "=m")
+ [(parallel [(match_operand 0 "memory_operand" "=k")
(match_operand 1 "gpc_reg_operand" "r")
(match_operand:GPR 2 "register_operand" "=&b")])]
""
@@ -8893,7 +8893,7 @@
(define_expand "reload_<mode>_load"
[(parallel [(match_operand 0 "gpc_reg_operand" "=r")
- (match_operand 1 "memory_operand" "m")
+ (match_operand 1 "memory_operand" "k")
(match_operand:GPR 2 "register_operand" "=b")])]
""
{
@@ -8907,7 +8907,7 @@
;; for vector registers and reg+reg or (reg+reg)&(-16) addressing to just an
;; index register for gpr registers.
(define_expand "reload_<RELOAD:mode>_<P:mptrsize>_store"
- [(parallel [(match_operand:RELOAD 0 "memory_operand" "m")
+ [(parallel [(match_operand:RELOAD 0 "memory_operand" "k")
(match_operand:RELOAD 1 "gpc_reg_operand" "wa")
(match_operand:P 2 "register_operand" "=b")])]
"<P:tptrsize>"
@@ -8918,7 +8918,7 @@
(define_expand "reload_<RELOAD:mode>_<P:mptrsize>_load"
[(parallel [(match_operand:RELOAD 0 "gpc_reg_operand" "wa")
- (match_operand:RELOAD 1 "memory_operand" "m")
+ (match_operand:RELOAD 1 "memory_operand" "k")
(match_operand:P 2 "register_operand" "=b")])]
"<P:tptrsize>"
{
@@ -9190,12 +9190,12 @@
(define_insn "*movdi_internal32"
[(set (match_operand:DI 0 "nonimmediate_operand"
- "=Y, r, r, m, ^d, ^d,
+ "=Y, r, r, k, ^d, ^d,
r, wY, Z, ^v, $v, ^wa,
wa, wa, v, wa, *i, v,
v")
(match_operand:DI 1 "input_operand"
- "r, Y, r, ^d, m, ^d,
+ "r, Y, r, ^d, k, ^d,
IJKnF, ^v, $v, wY, Z, ^wa,
Oj, wM, OjwM, Oj, wM, wS,
wB"))]
@@ -9281,7 +9281,7 @@
[(set (match_operand:DI 0 "nonimmediate_operand"
"=YZ, r, r,
r, r, r, r,
- m, ^d, ^d,
+ k, ^d, ^d,
wY, Z, $v, $v, ^wa,
wa, wa, v, wa, wa,
v, v,
@@ -9290,7 +9290,7 @@
(match_operand:DI 1 "input_operand"
"r, YZ, r,
I, L, eI, nF,
- ^d, m, ^d,
+ ^d, k, ^d,
^v, $v, wY, Z, ^wa,
Oj, wM, OjwM, Oj, wM,
wS, wB,
@@ -10777,7 +10777,7 @@
"la %0,%2@l(%1)")
(define_insn "*pltseq_tocsave_<mode>"
- [(set (match_operand:P 0 "memory_operand" "=m")
+ [(set (match_operand:P 0 "memory_operand" "=k")
(unspec:P [(match_operand:P 1 "gpc_reg_operand" "b")
(match_operand:P 2 "symbol_ref_operand" "s")
(match_operand:P 3 "" "")]
@@ -11538,7 +11538,7 @@
})
(define_insn "probe_stack_<mode>"
- [(set (match_operand:P 0 "memory_operand" "=m")
+ [(set (match_operand:P 0 "memory_operand" "=k")
(unspec:P [(const_int 0)] UNSPEC_PROBE_STACK))]
""
{
@@ -11926,8 +11926,8 @@
})
(define_insn "stack_protect_setsi"
- [(set (match_operand:SI 0 "memory_operand" "=m")
- (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
+ [(set (match_operand:SI 0 "memory_operand" "=k")
+ (unspec:SI [(match_operand:SI 1 "memory_operand" "k")] UNSPEC_SP_SET))
(set (match_scratch:SI 2 "=&r") (const_int 0))]
"TARGET_32BIT"
"lwz%U1%X1 %2,%1\;stw%U0%X0 %2,%0\;li %2,0"
@@ -11999,8 +11999,8 @@
(define_insn "stack_protect_testsi"
[(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
- (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
- (match_operand:SI 2 "memory_operand" "m,m")]
+ (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "k,k")
+ (match_operand:SI 2 "memory_operand" "k,k")]
UNSPEC_SP_TEST))
(set (match_scratch:SI 4 "=r,r") (const_int 0))
(clobber (match_scratch:SI 3 "=&r,&r"))]
@@ -13399,7 +13399,7 @@
(define_insn "*crsave"
[(match_parallel 0 "crsave_operation"
- [(set (match_operand:SI 1 "memory_operand" "=m")
+ [(set (match_operand:SI 1 "memory_operand" "=k")
(match_operand:SI 2 "gpc_reg_operand" "r"))])]
""
"stw %2,%1"
@@ -13407,7 +13407,7 @@
(define_insn "*stmw"
[(match_parallel 0 "stmw_operation"
- [(set (match_operand:SI 1 "memory_operand" "=m")
+ [(set (match_operand:SI 1 "memory_operand" "=k")
(match_operand:SI 2 "gpc_reg_operand" "r"))])]
"TARGET_MULTIPLE"
"stmw %2,%1"
@@ -13435,7 +13435,7 @@
[(clobber (reg:P LR_REGNO))
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 11))
- (set (match_operand:P 2 "memory_operand" "=m")
+ (set (match_operand:P 2 "memory_operand" "=k")
(match_operand:P 3 "gpc_reg_operand" "r"))])]
""
"bl %1"
@@ -13446,7 +13446,7 @@
[(clobber (reg:P LR_REGNO))
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 12))
- (set (match_operand:P 2 "memory_operand" "=m")
+ (set (match_operand:P 2 "memory_operand" "=k")
(match_operand:P 3 "gpc_reg_operand" "r"))])]
""
"bl %1"
@@ -13457,7 +13457,7 @@
[(clobber (reg:P LR_REGNO))
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 1))
- (set (match_operand:P 2 "memory_operand" "=m")
+ (set (match_operand:P 2 "memory_operand" "=k")
(match_operand:P 3 "gpc_reg_operand" "r"))])]
""
"bl %1"
@@ -13468,7 +13468,7 @@
[(clobber (reg:P LR_REGNO))
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 11))
- (set (match_operand:DF 2 "memory_operand" "=m")
+ (set (match_operand:DF 2 "memory_operand" "=k")
(match_operand:DF 3 "gpc_reg_operand" "d"))])]
""
"bl %1"
@@ -13479,7 +13479,7 @@
[(clobber (reg:P LR_REGNO))
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 12))
- (set (match_operand:DF 2 "memory_operand" "=m")
+ (set (match_operand:DF 2 "memory_operand" "=k")
(match_operand:DF 3 "gpc_reg_operand" "d"))])]
""
"bl %1"
@@ -13490,7 +13490,7 @@
[(clobber (reg:P LR_REGNO))
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 1))
- (set (match_operand:DF 2 "memory_operand" "=m")
+ (set (match_operand:DF 2 "memory_operand" "=k")
(match_operand:DF 3 "gpc_reg_operand" "d"))])]
""
"bl %1"
@@ -13576,7 +13576,7 @@
(define_insn "*lmw"
[(match_parallel 0 "lmw_operation"
[(set (match_operand:SI 1 "gpc_reg_operand" "=r")
- (match_operand:SI 2 "memory_operand" "m"))])]
+ (match_operand:SI 2 "memory_operand" "k"))])]
"TARGET_MULTIPLE"
"lmw %1,%2"
[(set_attr "type" "load")
@@ -13607,7 +13607,7 @@
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 11))
(set (match_operand:P 2 "gpc_reg_operand" "=r")
- (match_operand:P 3 "memory_operand" "m"))])]
+ (match_operand:P 3 "memory_operand" "k"))])]
""
"bl %1"
[(set_attr "type" "branch")])
@@ -13618,7 +13618,7 @@
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 12))
(set (match_operand:P 2 "gpc_reg_operand" "=r")
- (match_operand:P 3 "memory_operand" "m"))])]
+ (match_operand:P 3 "memory_operand" "k"))])]
""
"bl %1"
[(set_attr "type" "branch")])
@@ -13629,7 +13629,7 @@
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 1))
(set (match_operand:P 2 "gpc_reg_operand" "=r")
- (match_operand:P 3 "memory_operand" "m"))])]
+ (match_operand:P 3 "memory_operand" "k"))])]
""
"bl %1"
[(set_attr "type" "branch")])
@@ -13641,7 +13641,7 @@
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 11))
(set (match_operand:P 2 "gpc_reg_operand" "=r")
- (match_operand:P 3 "memory_operand" "m"))])]
+ (match_operand:P 3 "memory_operand" "k"))])]
""
"b %1"
[(set_attr "type" "branch")])
@@ -13653,7 +13653,7 @@
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 12))
(set (match_operand:P 2 "gpc_reg_operand" "=r")
- (match_operand:P 3 "memory_operand" "m"))])]
+ (match_operand:P 3 "memory_operand" "k"))])]
""
"b %1"
[(set_attr "type" "branch")])
@@ -13665,7 +13665,7 @@
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 1))
(set (match_operand:P 2 "gpc_reg_operand" "=r")
- (match_operand:P 3 "memory_operand" "m"))])]
+ (match_operand:P 3 "memory_operand" "k"))])]
""
"b %1"
[(set_attr "type" "branch")])
@@ -13677,7 +13677,7 @@
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 11))
(set (match_operand:DF 2 "gpc_reg_operand" "=d")
- (match_operand:DF 3 "memory_operand" "m"))])]
+ (match_operand:DF 3 "memory_operand" "k"))])]
""
"b %1"
[(set_attr "type" "branch")])
@@ -13689,7 +13689,7 @@
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 12))
(set (match_operand:DF 2 "gpc_reg_operand" "=d")
- (match_operand:DF 3 "memory_operand" "m"))])]
+ (match_operand:DF 3 "memory_operand" "k"))])]
""
"b %1"
[(set_attr "type" "branch")])
@@ -13701,7 +13701,7 @@
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 1))
(set (match_operand:DF 2 "gpc_reg_operand" "=d")
- (match_operand:DF 3 "memory_operand" "m"))])]
+ (match_operand:DF 3 "memory_operand" "k"))])]
""
"b %1"
[(set_attr "type" "branch")])
@@ -13712,7 +13712,7 @@
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 11))
(set (match_operand:DF 2 "gpc_reg_operand" "=d")
- (match_operand:DF 3 "memory_operand" "m"))])]
+ (match_operand:DF 3 "memory_operand" "k"))])]
""
"b %1"
[(set_attr "type" "branch")])
@@ -13723,7 +13723,7 @@
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 1))
(set (match_operand:DF 2 "gpc_reg_operand" "=d")
- (match_operand:DF 3 "memory_operand" "m"))])]
+ (match_operand:DF 3 "memory_operand" "k"))])]
""
"b %1"
[(set_attr "type" "branch")])
@@ -15184,7 +15184,7 @@
;; ROP mitigation instructions.
(define_insn "hashst"
- [(set (match_operand:DI 0 "simple_offsettable_mem_operand" "=m")
+ [(set (match_operand:DI 0 "simple_offsettable_mem_operand" "=k")
(unspec_volatile:DI [(match_operand:DI 1 "int_reg_operand" "r")]
UNSPEC_HASHST))]
"TARGET_POWER10 && rs6000_rop_protect"
@@ -15198,7 +15198,7 @@
(define_insn "hashchk"
[(unspec_volatile [(match_operand:DI 0 "int_reg_operand" "r")
- (match_operand:DI 1 "simple_offsettable_mem_operand" "m")]
+ (match_operand:DI 1 "simple_offsettable_mem_operand" "k")]
UNSPEC_HASHCHK)]
"TARGET_POWER10 && rs6000_rop_protect"
{
diff --git a/gcc/testsuite/gcc.target/powerpc/pr98519.c b/gcc/testsuite/gcc.target/powerpc/pr98519.c
new file mode 100644
index 00000000000..25918bac3ed
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr98519.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
+
+/* Compile with -mcpu=power10. The lxsd instruction should not be replaced
+ with a plxsd. */
+typedef vector double vf64_t;
+
+static double test_f64[16];
+
+vf64_t
+bug (void)
+{
+ vf64_t j0;
+ __asm__("lxsd%X1 %0,%1;" : "=v" (j0) : "m" (test_f64));
+ return j0;
+}
+
+/* { dg-final { scan-assembler {\mlxsd\M} } } */
+/* { dg-final { scan-assembler-not {\mplxsd\M} } } */
^ permalink raw reply [flat|nested] 4+ messages in thread
* [gcc(refs/users/meissner/heads/work062)] Do not allow prefixed loads/stores in PowerPC asm.
@ 2021-08-02 2:37 Michael Meissner
0 siblings, 0 replies; 4+ messages in thread
From: Michael Meissner @ 2021-08-02 2:37 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:2744703d9bbaf0e13d33f69c5bcfa0e46d78f74b
commit 2744703d9bbaf0e13d33f69c5bcfa0e46d78f74b
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Sun Aug 1 22:36:50 2021 -0400
Do not allow prefixed loads/stores in PowerPC asm.
The PowerPC has noraml loads and stores and then it has prefixed loads and
stores. The prefixed loads and stores have different names and format
than the normal loads and stores. The patch changes the 'm' constraint
from returning true for all valid memory insns to return true for all
valid non-prefixed memory insns. This allows __asm__ code to continue to
use the "m" constraint without getting assembler errors due to the non
prefixed instruction was being used.
I use the constraint "k" (which was unused) to be a replacement for the
"m" constraint. All of the mov insns and extend insns from memory were
changed to use the "k" constraint instead of the "m" constraint.
2021-07-31 Michael Meissner <meissner@linux.ibm.com>
gcc/
PR target/98519
* config/rs6000/constraints.md (top level): Adjust comment about
the available unused constraints.
(constraint "m"). New constraint.
* config/rs6000/rs6000.h (TARGET_MEM_CONSTRAINT): Define, making
'k' the new memory cosntraint.
* config/rs6000/rs6000.md (ptrm): Use "k" instead of "m".
(zero_extendqi<mode>2): Likewise.
(zero_extendhi<mode>2): Likewise.
(zero_extendsi<mode>2): Likewise.
(extendhi<mode>2): Likewise.
(signbit<mode>2_dm_mem): Likewise.
(floatdidf2_mem): Likewise.
(floatunsdidf2_mem): Likewise.
(floatdisf2_mem): Likewise.
(floatunsdisf2_mem): Likewise.
(movsi_internal1): Likewise.
(movdi_from_sf_zero_ext): Likewise.
(mov<mode>_internal, QHI iterator): Likewise.
(movsf_hardfloat): Likewise.
(movsd_hardfloat): Likewise.
(mov<mode>_softfloat): Likewise.
(mov<mode>_hardfloat32): Likewise.
(mov<mode>_hardfloat64): Likewise.
(mov<mode>_64bit_dm): Likewise.
(movtd_64bit_nodm): Likewise.
(mov<mode>_32bit. FMOVE128 iterator): Likewise.
(extenddf<mode>2, IBM128 iterator): Likewise.
(extendtf<mode>2): Likewise.
(reload_<mode>_load): Likewise.
(reload_<RELOAD:mode>_<P:mptrsize>_load): Likewise.
(movdi_internal32): Likewise.
(movdi_internal64): Likewise.
(pltseq_tocsave_<mode>): Likewise.
(probe_stack_<mode>): Likewise.
(stack_protect_setsi): Likewise.
(stack_protect_testsi): Likewise.
(crsave): Likewise.
(stmw): Likewise.
(save_gpregs_<mode>_r11): Likewise.
(save_gpregs_<mode>_r12): Likewise.
(save_gpregs_<mode>_r1): Likewise.
(save_fpregs_<mode>_r11): Likewise.
(save_fpregs_<mode>_r12): Likewise.
(save_fpregs_<mode>_r1): Likewise.
(mtcrfsi): Likewise.
(restore_gpregs_<mode>_r11): Likewise.
(restore_gpregs_<mode>_r12): Likewise.
(restore_gpregs_<mode>_r1): Likewise.
(return_and_restore_gpregs): Likewise.
(return_and_restore_fpregs): Likewise.
(hashst): Likewise.
(hashchk): Likewise.
gcc/testsuite/
PR target/98519
* gcc.target/powerpc/pr98519.c: New test.
Diff:
---
gcc/config/rs6000/constraints.md | 10 +-
gcc/config/rs6000/rs6000.h | 7 ++
gcc/config/rs6000/rs6000.md | 148 ++++++++++++++---------------
gcc/testsuite/gcc.target/powerpc/pr98519.c | 20 ++++
4 files changed, 110 insertions(+), 75 deletions(-)
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index 561ce9797af..a0a3cdb33a8 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -17,7 +17,7 @@
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
-;; Available constraint letters: e k q t u A B C D S T
+;; Available constraint letters: q t u A B C D S T
;; Register constraints
@@ -65,6 +65,14 @@
(define_register_constraint "l" "LINK_REGS"
"The link register, @code{lr}.")
+; This defines 'm' as normal memory constraint. This is only possible
+; since the standard memory constraint is re-defined in rs6000.h using
+; the TARGET_MEM_CONSTRAINT macro (to be k).
+(define_memory_constraint "m"
+ "Matches the most general non-prefixed memory address, suitable for asm."
+ (and (match_code "mem")
+ (not (match_operand 0 "prefixed_memory"))))
+
(define_register_constraint "x" "CR0_REGS"
"Condition register field 0, @code{cr0}.")
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 4ca6372435d..14b99fb0edb 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -1248,6 +1248,13 @@ enum r6000_reg_class_enum {
extern enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX];
+/* This definition replaces the formerly used 'm' constraint with a
+ different constraint letter in order to avoid changing semantics of
+ the 'm' constraint when accepting new address formats in
+ TARGET_LEGITIMATE_ADDRESS_P. The constraint letter defined here
+ must not be used in insn definitions or inline assemblies. */
+#define TARGET_MEM_CONSTRAINT 'k'
+
/* The class value for index registers, and the one for base regs. */
#define INDEX_REG_CLASS GENERAL_REGS
#define BASE_REG_CLASS BASE_REGS
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index a84438f8545..38f235bbc2c 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -728,7 +728,7 @@
(define_mode_attr ptrload [(SI "lwz")
(DI "ld")])
-(define_mode_attr ptrm [(SI "m")
+(define_mode_attr ptrm [(SI "k")
(DI "Y")])
(define_mode_attr rreg [(SF "f")
@@ -836,7 +836,7 @@
(define_insn "zero_extendqi<mode>2"
[(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,r,^wa,^v")
- (zero_extend:EXTQI (match_operand:QI 1 "reg_or_mem_operand" "m,r,Z,v")))]
+ (zero_extend:EXTQI (match_operand:QI 1 "reg_or_mem_operand" "k,r,Z,v")))]
""
"@
lbz%U1%X1 %0,%1
@@ -890,7 +890,7 @@
(define_insn "zero_extendhi<mode>2"
[(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r,^wa,^v")
- (zero_extend:EXTHI (match_operand:HI 1 "reg_or_mem_operand" "m,r,Z,v")))]
+ (zero_extend:EXTHI (match_operand:HI 1 "reg_or_mem_operand" "k,r,Z,v")))]
""
"@
lhz%U1%X1 %0,%1
@@ -944,7 +944,7 @@
(define_insn "zero_extendsi<mode>2"
[(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r,d,wa,wa,r,wa")
- (zero_extend:EXTSI (match_operand:SI 1 "reg_or_mem_operand" "m,r,Z,Z,r,wa,wa")))]
+ (zero_extend:EXTSI (match_operand:SI 1 "reg_or_mem_operand" "k,r,Z,Z,r,wa,wa")))]
""
"@
lwz%U1%X1 %0,%1
@@ -1059,7 +1059,7 @@
(define_insn "*extendhi<mode>2"
[(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r,?*v,?*v")
- (sign_extend:EXTHI (match_operand:HI 1 "reg_or_mem_operand" "m,r,Z,v")))]
+ (sign_extend:EXTHI (match_operand:HI 1 "reg_or_mem_operand" "k,r,Z,v")))]
""
"@
lha%U1%X1 %0,%1
@@ -5140,7 +5140,7 @@
;; little endian, we have to load the 2nd double-word to get the sign bit.
(define_insn_and_split "*signbit<mode>2_dm_mem"
[(set (match_operand:DI 0 "gpc_reg_operand" "=b")
- (unspec:DI [(match_operand:SIGNBIT 1 "memory_operand" "m")]
+ (unspec:DI [(match_operand:SIGNBIT 1 "memory_operand" "k")]
UNSPEC_SIGNBIT))]
"TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
"#"
@@ -6656,7 +6656,7 @@
(define_insn_and_split "*floatdidf2_mem"
[(set (match_operand:DF 0 "gpc_reg_operand" "=d,wa")
- (float:DF (match_operand:DI 1 "memory_operand" "m,Z")))
+ (float:DF (match_operand:DI 1 "memory_operand" "k,Z")))
(clobber (match_scratch:DI 2 "=d,wa"))]
"TARGET_HARD_FLOAT && TARGET_FCFID"
"#"
@@ -6685,7 +6685,7 @@
(define_insn_and_split "*floatunsdidf2_mem"
[(set (match_operand:DF 0 "gpc_reg_operand" "=d,wa")
- (unsigned_float:DF (match_operand:DI 1 "memory_operand" "m,Z")))
+ (unsigned_float:DF (match_operand:DI 1 "memory_operand" "k,Z")))
(clobber (match_scratch:DI 2 "=d,wa"))]
"TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))"
"#"
@@ -6729,7 +6729,7 @@
(define_insn_and_split "*floatdisf2_mem"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f,wa,wa")
- (float:SF (match_operand:DI 1 "memory_operand" "m,m,Z")))
+ (float:SF (match_operand:DI 1 "memory_operand" "k,k,Z")))
(clobber (match_scratch:DI 2 "=d,d,wa"))]
"TARGET_HARD_FLOAT && TARGET_FCFIDS"
"#"
@@ -6810,7 +6810,7 @@
(define_insn_and_split "*floatunsdisf2_mem"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f,wa,wa")
- (unsigned_float:SF (match_operand:DI 1 "memory_operand" "m,m,Z")))
+ (unsigned_float:SF (match_operand:DI 1 "memory_operand" "k,k,Z")))
(clobber (match_scratch:DI 2 "=d,d,wa"))]
"TARGET_HARD_FLOAT && TARGET_FCFIDUS"
"#"
@@ -7297,7 +7297,7 @@
[(set (match_operand:SI 0 "nonimmediate_operand"
"=r, r,
r, d, v,
- m, Z, Z,
+ k, Z, Z,
r, r, r, r,
wa, wa, wa, v,
wa, v, v,
@@ -7305,7 +7305,7 @@
r, *h, *h")
(match_operand:SI 1 "input_operand"
"r, U,
- m, Z, Z,
+ k, Z, Z,
r, d, v,
I, L, eI, n,
wa, O, wM, wB,
@@ -7388,11 +7388,11 @@
(define_insn_and_split "movsi_from_sf"
[(set (match_operand:SI 0 "nonimmediate_operand"
- "=r, r, ?*d, ?*v, m,
- m, wY, Z, r, ?*wa,
+ "=r, r, ?*d, ?*v, k,
+ k, wY, Z, r, ?*wa,
wa")
(unspec:SI [(match_operand:SF 1 "input_operand"
- "r, m, Z, Z, r,
+ "r, k, Z, Z, r,
f, v, wa, wa, wa,
r")]
UNSPEC_SI_FROM_SF))
@@ -7454,7 +7454,7 @@
?v, wa")
(zero_extend:DI
(unspec:SI [(match_operand:SF 1 "input_operand"
- "r, m, Z, Z, wa,
+ "r, k, Z, Z, wa,
wa, r")]
UNSPEC_SI_FROM_SF)))
(clobber (match_scratch:V4SF 2
@@ -7586,11 +7586,11 @@
;; MTVSRWZ MF%1 MT%1 NOP
(define_insn "*mov<mode>_internal"
[(set (match_operand:QHI 0 "nonimmediate_operand"
- "=r, r, wa, m, Z, r,
+ "=r, r, wa, k, Z, r,
wa, wa, wa, v, ?v, r,
wa, r, *c*l, *h")
(match_operand:QHI 1 "input_operand"
- "r, m, Z, r, wa, i,
+ "r, k, Z, r, wa, i,
wa, O, wM, wB, wS, wa,
r, *h, r, 0"))]
"gpc_reg_operand (operands[0], <MODE>mode)
@@ -7727,11 +7727,11 @@
(define_insn "movsf_hardfloat"
[(set (match_operand:SF 0 "nonimmediate_operand"
- "=!r, f, v, wa, m, wY,
- Z, m, wa, !r, f, wa,
+ "=!r, f, v, wa, k, wY,
+ Z, k, wa, !r, f, wa,
!r, *c*l, !r, *h")
(match_operand:SF 1 "input_operand"
- "m, m, wY, Z, f, v,
+ "k, k, wY, Z, f, v,
wa, r, j, j, f, wa,
r, r, *h, 0"))]
"(register_operand (operands[0], SFmode)
@@ -7769,10 +7769,10 @@
;; FMR MR MT%0 MF%1 NOP
(define_insn "movsd_hardfloat"
[(set (match_operand:SD 0 "nonimmediate_operand"
- "=!r, d, m, Z, ?d, ?r,
+ "=!r, d, k, Z, ?d, ?r,
f, !r, *c*l, !r, *h")
(match_operand:SD 1 "input_operand"
- "m, Z, r, wx, r, d,
+ "k, Z, r, wx, r, d,
f, r, r, *h, 0"))]
"(register_operand (operands[0], SDmode)
|| register_operand (operands[1], SDmode))
@@ -7800,11 +7800,11 @@
;; LIS G-const. F/n-const NOP
(define_insn "*mov<mode>_softfloat"
[(set (match_operand:FMOVE32 0 "nonimmediate_operand"
- "=r, *c*l, r, r, m, r,
+ "=r, *c*l, r, r, k, r,
r, r, r, *h")
(match_operand:FMOVE32 1 "input_operand"
- "r, r, *h, m, r, I,
+ "r, r, *h, k, r, I,
L, G, Fn, 0"))]
"(gpc_reg_operand (operands[0], <MODE>mode)
@@ -7848,10 +7848,10 @@
;; STXSIWX GPR->VSX VSX->GPR GPR->GPR
(define_insn_and_split "movsf_from_si"
[(set (match_operand:SF 0 "nonimmediate_operand"
- "=!r, f, v, wa, m, Z,
+ "=!r, f, v, wa, k, Z,
Z, wa, ?r, !r")
(unspec:SF [(match_operand:SI 1 "input_operand"
- "m, m, wY, Z, r, f,
+ "k, k, wY, Z, r, f,
wa, r, wa, r")]
UNSPEC_SF_FROM_SI))
(clobber (match_scratch:DI 2
@@ -8028,11 +8028,11 @@
(define_insn "*mov<mode>_hardfloat32"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
- "=m, d, d, <f64_p9>, wY,
+ "=k, d, d, <f64_p9>, wY,
<f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
Y, r, !r")
(match_operand:FMOVE64 1 "input_operand"
- "d, m, d, wY, <f64_p9>,
+ "d, k, d, wY, <f64_p9>,
Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>,
r, Y, r"))]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT
@@ -8095,12 +8095,12 @@
(define_insn "*mov<mode>_hardfloat64"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
- "=m, d, d, <f64_p9>, wY,
+ "=k, d, d, <f64_p9>, wY,
<f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
YZ, r, !r, *c*l, !r,
*h, r, <f64_dm>")
(match_operand:FMOVE64 1 "input_operand"
- "d, m, d, wY, <f64_p9>,
+ "d, k, d, wY, <f64_p9>,
Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>,
r, YZ, r, r, *h,
0, <f64_dm>, r"))]
@@ -8193,11 +8193,11 @@
(define_insn_and_split "*mov<mode>_64bit_dm"
[(set (match_operand:FMOVE128_FPR 0 "nonimmediate_operand"
- "=m, d, d, d, Y,
+ "=k, d, d, d, Y,
r, r, r, r, d")
(match_operand:FMOVE128_FPR 1 "input_operand"
- "d, m, d, <zero_fp>, r,
+ "d, k, d, <zero_fp>, r,
<zero_fp>, Y, r, d, r"))]
"TARGET_HARD_FLOAT && TARGET_POWERPC64 && FLOAT128_2REG_P (<MODE>mode)
@@ -8217,8 +8217,8 @@
(set_attr "num_insns" "2")])
(define_insn_and_split "*movtd_64bit_nodm"
- [(set (match_operand:TD 0 "nonimmediate_operand" "=m,d,d,Y,r,r")
- (match_operand:TD 1 "input_operand" "d,m,d,r,Y,r"))]
+ [(set (match_operand:TD 0 "nonimmediate_operand" "=k,d,d,Y,r,r")
+ (match_operand:TD 1 "input_operand" "d,k,d,r,Y,r"))]
"TARGET_HARD_FLOAT && TARGET_POWERPC64 && !WORDS_BIG_ENDIAN
&& (gpc_reg_operand (operands[0], TDmode)
|| gpc_reg_operand (operands[1], TDmode))"
@@ -8234,8 +8234,8 @@
(set_attr "num_insns" "2,2,2,3,3,2")])
(define_insn_and_split "*mov<mode>_32bit"
- [(set (match_operand:FMOVE128_FPR 0 "nonimmediate_operand" "=m,d,d,d,Y,r,r")
- (match_operand:FMOVE128_FPR 1 "input_operand" "d,m,d,<zero_fp>,r,<zero_fp>Y,r"))]
+ [(set (match_operand:FMOVE128_FPR 0 "nonimmediate_operand" "=k,d,d,d,Y,r,r")
+ (match_operand:FMOVE128_FPR 1 "input_operand" "d,k,d,<zero_fp>,r,<zero_fp>Y,r"))]
"TARGET_HARD_FLOAT && !TARGET_POWERPC64
&& (FLOAT128_2REG_P (<MODE>mode)
|| int_reg_operand_not_pseudo (operands[0], <MODE>mode)
@@ -8303,7 +8303,7 @@
[(set (match_operand:IBM128 0 "gpc_reg_operand" "=d,d,&d")
(float_extend:IBM128
(match_operand:DF 1 "nonimmediate_operand" "d,m,d")))
- (use (match_operand:DF 2 "nonimmediate_operand" "m,m,d"))]
+ (use (match_operand:DF 2 "nonimmediate_operand" "k,k,d"))]
"!TARGET_VSX && TARGET_HARD_FLOAT
&& TARGET_LONG_DOUBLE_128 && FLOAT128_IBM_P (<MODE>mode)"
"#"
@@ -8882,7 +8882,7 @@
;; Reload patterns to support gpr load/store with misaligned mem.
;; and multiple gpr load/store at offset >= 0xfffc
(define_expand "reload_<mode>_store"
- [(parallel [(match_operand 0 "memory_operand" "=m")
+ [(parallel [(match_operand 0 "memory_operand" "=k")
(match_operand 1 "gpc_reg_operand" "r")
(match_operand:GPR 2 "register_operand" "=&b")])]
""
@@ -8893,7 +8893,7 @@
(define_expand "reload_<mode>_load"
[(parallel [(match_operand 0 "gpc_reg_operand" "=r")
- (match_operand 1 "memory_operand" "m")
+ (match_operand 1 "memory_operand" "k")
(match_operand:GPR 2 "register_operand" "=b")])]
""
{
@@ -8907,7 +8907,7 @@
;; for vector registers and reg+reg or (reg+reg)&(-16) addressing to just an
;; index register for gpr registers.
(define_expand "reload_<RELOAD:mode>_<P:mptrsize>_store"
- [(parallel [(match_operand:RELOAD 0 "memory_operand" "m")
+ [(parallel [(match_operand:RELOAD 0 "memory_operand" "k")
(match_operand:RELOAD 1 "gpc_reg_operand" "wa")
(match_operand:P 2 "register_operand" "=b")])]
"<P:tptrsize>"
@@ -8918,7 +8918,7 @@
(define_expand "reload_<RELOAD:mode>_<P:mptrsize>_load"
[(parallel [(match_operand:RELOAD 0 "gpc_reg_operand" "wa")
- (match_operand:RELOAD 1 "memory_operand" "m")
+ (match_operand:RELOAD 1 "memory_operand" "k")
(match_operand:P 2 "register_operand" "=b")])]
"<P:tptrsize>"
{
@@ -9190,12 +9190,12 @@
(define_insn "*movdi_internal32"
[(set (match_operand:DI 0 "nonimmediate_operand"
- "=Y, r, r, m, ^d, ^d,
+ "=Y, r, r, k, ^d, ^d,
r, wY, Z, ^v, $v, ^wa,
wa, wa, v, wa, *i, v,
v")
(match_operand:DI 1 "input_operand"
- "r, Y, r, ^d, m, ^d,
+ "r, Y, r, ^d, k, ^d,
IJKnF, ^v, $v, wY, Z, ^wa,
Oj, wM, OjwM, Oj, wM, wS,
wB"))]
@@ -9281,7 +9281,7 @@
[(set (match_operand:DI 0 "nonimmediate_operand"
"=YZ, r, r,
r, r, r, r,
- m, ^d, ^d,
+ k, ^d, ^d,
wY, Z, $v, $v, ^wa,
wa, wa, v, wa, wa,
v, v,
@@ -9290,7 +9290,7 @@
(match_operand:DI 1 "input_operand"
"r, YZ, r,
I, L, eI, nF,
- ^d, m, ^d,
+ ^d, k, ^d,
^v, $v, wY, Z, ^wa,
Oj, wM, OjwM, Oj, wM,
wS, wB,
@@ -10777,7 +10777,7 @@
"la %0,%2@l(%1)")
(define_insn "*pltseq_tocsave_<mode>"
- [(set (match_operand:P 0 "memory_operand" "=m")
+ [(set (match_operand:P 0 "memory_operand" "=k")
(unspec:P [(match_operand:P 1 "gpc_reg_operand" "b")
(match_operand:P 2 "symbol_ref_operand" "s")
(match_operand:P 3 "" "")]
@@ -11538,7 +11538,7 @@
})
(define_insn "probe_stack_<mode>"
- [(set (match_operand:P 0 "memory_operand" "=m")
+ [(set (match_operand:P 0 "memory_operand" "=k")
(unspec:P [(const_int 0)] UNSPEC_PROBE_STACK))]
""
{
@@ -11926,8 +11926,8 @@
})
(define_insn "stack_protect_setsi"
- [(set (match_operand:SI 0 "memory_operand" "=m")
- (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
+ [(set (match_operand:SI 0 "memory_operand" "=k")
+ (unspec:SI [(match_operand:SI 1 "memory_operand" "k")] UNSPEC_SP_SET))
(set (match_scratch:SI 2 "=&r") (const_int 0))]
"TARGET_32BIT"
"lwz%U1%X1 %2,%1\;stw%U0%X0 %2,%0\;li %2,0"
@@ -11999,8 +11999,8 @@
(define_insn "stack_protect_testsi"
[(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
- (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
- (match_operand:SI 2 "memory_operand" "m,m")]
+ (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "k,k")
+ (match_operand:SI 2 "memory_operand" "k,k")]
UNSPEC_SP_TEST))
(set (match_scratch:SI 4 "=r,r") (const_int 0))
(clobber (match_scratch:SI 3 "=&r,&r"))]
@@ -13399,7 +13399,7 @@
(define_insn "*crsave"
[(match_parallel 0 "crsave_operation"
- [(set (match_operand:SI 1 "memory_operand" "=m")
+ [(set (match_operand:SI 1 "memory_operand" "=k")
(match_operand:SI 2 "gpc_reg_operand" "r"))])]
""
"stw %2,%1"
@@ -13407,7 +13407,7 @@
(define_insn "*stmw"
[(match_parallel 0 "stmw_operation"
- [(set (match_operand:SI 1 "memory_operand" "=m")
+ [(set (match_operand:SI 1 "memory_operand" "=k")
(match_operand:SI 2 "gpc_reg_operand" "r"))])]
"TARGET_MULTIPLE"
"stmw %2,%1"
@@ -13435,7 +13435,7 @@
[(clobber (reg:P LR_REGNO))
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 11))
- (set (match_operand:P 2 "memory_operand" "=m")
+ (set (match_operand:P 2 "memory_operand" "=k")
(match_operand:P 3 "gpc_reg_operand" "r"))])]
""
"bl %1"
@@ -13446,7 +13446,7 @@
[(clobber (reg:P LR_REGNO))
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 12))
- (set (match_operand:P 2 "memory_operand" "=m")
+ (set (match_operand:P 2 "memory_operand" "=k")
(match_operand:P 3 "gpc_reg_operand" "r"))])]
""
"bl %1"
@@ -13457,7 +13457,7 @@
[(clobber (reg:P LR_REGNO))
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 1))
- (set (match_operand:P 2 "memory_operand" "=m")
+ (set (match_operand:P 2 "memory_operand" "=k")
(match_operand:P 3 "gpc_reg_operand" "r"))])]
""
"bl %1"
@@ -13468,7 +13468,7 @@
[(clobber (reg:P LR_REGNO))
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 11))
- (set (match_operand:DF 2 "memory_operand" "=m")
+ (set (match_operand:DF 2 "memory_operand" "=k")
(match_operand:DF 3 "gpc_reg_operand" "d"))])]
""
"bl %1"
@@ -13479,7 +13479,7 @@
[(clobber (reg:P LR_REGNO))
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 12))
- (set (match_operand:DF 2 "memory_operand" "=m")
+ (set (match_operand:DF 2 "memory_operand" "=k")
(match_operand:DF 3 "gpc_reg_operand" "d"))])]
""
"bl %1"
@@ -13490,7 +13490,7 @@
[(clobber (reg:P LR_REGNO))
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 1))
- (set (match_operand:DF 2 "memory_operand" "=m")
+ (set (match_operand:DF 2 "memory_operand" "=k")
(match_operand:DF 3 "gpc_reg_operand" "d"))])]
""
"bl %1"
@@ -13576,7 +13576,7 @@
(define_insn "*lmw"
[(match_parallel 0 "lmw_operation"
[(set (match_operand:SI 1 "gpc_reg_operand" "=r")
- (match_operand:SI 2 "memory_operand" "m"))])]
+ (match_operand:SI 2 "memory_operand" "k"))])]
"TARGET_MULTIPLE"
"lmw %1,%2"
[(set_attr "type" "load")
@@ -13607,7 +13607,7 @@
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 11))
(set (match_operand:P 2 "gpc_reg_operand" "=r")
- (match_operand:P 3 "memory_operand" "m"))])]
+ (match_operand:P 3 "memory_operand" "k"))])]
""
"bl %1"
[(set_attr "type" "branch")])
@@ -13618,7 +13618,7 @@
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 12))
(set (match_operand:P 2 "gpc_reg_operand" "=r")
- (match_operand:P 3 "memory_operand" "m"))])]
+ (match_operand:P 3 "memory_operand" "k"))])]
""
"bl %1"
[(set_attr "type" "branch")])
@@ -13629,7 +13629,7 @@
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 1))
(set (match_operand:P 2 "gpc_reg_operand" "=r")
- (match_operand:P 3 "memory_operand" "m"))])]
+ (match_operand:P 3 "memory_operand" "k"))])]
""
"bl %1"
[(set_attr "type" "branch")])
@@ -13641,7 +13641,7 @@
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 11))
(set (match_operand:P 2 "gpc_reg_operand" "=r")
- (match_operand:P 3 "memory_operand" "m"))])]
+ (match_operand:P 3 "memory_operand" "k"))])]
""
"b %1"
[(set_attr "type" "branch")])
@@ -13653,7 +13653,7 @@
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 12))
(set (match_operand:P 2 "gpc_reg_operand" "=r")
- (match_operand:P 3 "memory_operand" "m"))])]
+ (match_operand:P 3 "memory_operand" "k"))])]
""
"b %1"
[(set_attr "type" "branch")])
@@ -13665,7 +13665,7 @@
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 1))
(set (match_operand:P 2 "gpc_reg_operand" "=r")
- (match_operand:P 3 "memory_operand" "m"))])]
+ (match_operand:P 3 "memory_operand" "k"))])]
""
"b %1"
[(set_attr "type" "branch")])
@@ -13677,7 +13677,7 @@
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 11))
(set (match_operand:DF 2 "gpc_reg_operand" "=d")
- (match_operand:DF 3 "memory_operand" "m"))])]
+ (match_operand:DF 3 "memory_operand" "k"))])]
""
"b %1"
[(set_attr "type" "branch")])
@@ -13689,7 +13689,7 @@
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 12))
(set (match_operand:DF 2 "gpc_reg_operand" "=d")
- (match_operand:DF 3 "memory_operand" "m"))])]
+ (match_operand:DF 3 "memory_operand" "k"))])]
""
"b %1"
[(set_attr "type" "branch")])
@@ -13701,7 +13701,7 @@
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 1))
(set (match_operand:DF 2 "gpc_reg_operand" "=d")
- (match_operand:DF 3 "memory_operand" "m"))])]
+ (match_operand:DF 3 "memory_operand" "k"))])]
""
"b %1"
[(set_attr "type" "branch")])
@@ -13712,7 +13712,7 @@
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 11))
(set (match_operand:DF 2 "gpc_reg_operand" "=d")
- (match_operand:DF 3 "memory_operand" "m"))])]
+ (match_operand:DF 3 "memory_operand" "k"))])]
""
"b %1"
[(set_attr "type" "branch")])
@@ -13723,7 +13723,7 @@
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 1))
(set (match_operand:DF 2 "gpc_reg_operand" "=d")
- (match_operand:DF 3 "memory_operand" "m"))])]
+ (match_operand:DF 3 "memory_operand" "k"))])]
""
"b %1"
[(set_attr "type" "branch")])
@@ -15184,7 +15184,7 @@
;; ROP mitigation instructions.
(define_insn "hashst"
- [(set (match_operand:DI 0 "simple_offsettable_mem_operand" "=m")
+ [(set (match_operand:DI 0 "simple_offsettable_mem_operand" "=k")
(unspec_volatile:DI [(match_operand:DI 1 "int_reg_operand" "r")]
UNSPEC_HASHST))]
"TARGET_POWER10 && rs6000_rop_protect"
@@ -15198,7 +15198,7 @@
(define_insn "hashchk"
[(unspec_volatile [(match_operand:DI 0 "int_reg_operand" "r")
- (match_operand:DI 1 "simple_offsettable_mem_operand" "m")]
+ (match_operand:DI 1 "simple_offsettable_mem_operand" "k")]
UNSPEC_HASHCHK)]
"TARGET_POWER10 && rs6000_rop_protect"
{
diff --git a/gcc/testsuite/gcc.target/powerpc/pr98519.c b/gcc/testsuite/gcc.target/powerpc/pr98519.c
new file mode 100644
index 00000000000..25918bac3ed
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr98519.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
+
+/* Compile with -mcpu=power10. The lxsd instruction should not be replaced
+ with a plxsd. */
+typedef vector double vf64_t;
+
+static double test_f64[16];
+
+vf64_t
+bug (void)
+{
+ vf64_t j0;
+ __asm__("lxsd%X1 %0,%1;" : "=v" (j0) : "m" (test_f64));
+ return j0;
+}
+
+/* { dg-final { scan-assembler {\mlxsd\M} } } */
+/* { dg-final { scan-assembler-not {\mplxsd\M} } } */
^ permalink raw reply [flat|nested] 4+ messages in thread
* [gcc(refs/users/meissner/heads/work062)] Do not allow prefixed loads/stores in PowerPC asm.
@ 2021-07-31 4:00 Michael Meissner
0 siblings, 0 replies; 4+ messages in thread
From: Michael Meissner @ 2021-07-31 4:00 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:93df1f7c4ed07ed5db522f570a5bfca80998ad30
commit 93df1f7c4ed07ed5db522f570a5bfca80998ad30
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Jul 30 23:59:52 2021 -0400
Do not allow prefixed loads/stores in PowerPC asm.
The PowerPC has noraml loads and stores and then it has prefixed loads and
stores. The prefixed loads and stores have different names and format
than the normal loads and stores. This patch adds a new hook that is run
in the passes before reload to ensure that no prefixed memory is generated
by optimizations.
This patch contains the PowerPC bits to ensure that prefixed addresses are
not passed as asm operands.
2021-07-31 Michael Meissner <meissner@linux.ibm.com>
gcc/
PR target/98519
* config/rs6000/rs6000.c (rs6000_asm_operand_p): New function.
(TARGET_MD_ASM_OPERAND_P): Override md_asm_operand_p hook.
gcc/testsuite/
PR target/98519
* gcc.target/powerpc/pr98519.c: New test.
Diff:
---
gcc/config/rs6000/rs6000.c | 28 ++++++++++++++++++++++++++++
gcc/testsuite/gcc.target/powerpc/pr98519.c | 20 ++++++++++++++++++++
2 files changed, 48 insertions(+)
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 2de5a96e1b6..73e87c3cbc6 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -1196,6 +1196,8 @@ static bool rs6000_secondary_reload_move (enum rs6000_reg_type,
bool);
rtl_opt_pass *make_pass_analyze_swaps (gcc::context*);
+static bool rs6000_asm_operand_p (rtx, const char *, const char **);
+
/* Hash table stuff for keeping track of TOC entries. */
struct GTY((for_user)) toc_hash_struct
@@ -1639,6 +1641,9 @@ static const struct attribute_spec rs6000_attribute_table[] =
#undef TARGET_LEGITIMATE_ADDRESS_P
#define TARGET_LEGITIMATE_ADDRESS_P rs6000_legitimate_address_p
+#undef TARGET_MD_ASM_OPERAND_P
+#define TARGET_MD_ASM_OPERAND_P rs6000_asm_operand_p
+
#undef TARGET_MODE_DEPENDENT_ADDRESS_P
#define TARGET_MODE_DEPENDENT_ADDRESS_P rs6000_mode_dependent_address_p
@@ -9921,6 +9926,29 @@ rs6000_offsettable_memref_p (rtx op, machine_mode reg_mode, bool strict)
strict, worst_case);
}
+/* Add additional constraints for asm operands. We use it to prevent
+ prefixed loads/stores from appearing in normal asm statements.
+
+ At the moment, we just ban all prefixed loads/stores. If we add a
+ constraint specifically for prefixed loads/stores, we might need to scan the
+ constraint string for that constraint. */
+
+static bool
+rs6000_asm_operand_p (rtx op,
+ const char *constraint ATTRIBUTE_UNUSED,
+ const char **constraints ATTRIBUTE_UNUSED)
+{
+ if (TARGET_PREFIXED && MEM_P (op))
+ {
+ rtx addr = XEXP (op, 0);
+ machine_mode mode = GET_MODE (op);
+ if (address_is_prefixed (addr, mode, NON_PREFIXED_DEFAULT))
+ return false;
+ }
+
+ return true;
+}
+
/* Determine the reassociation width to be used in reassociate_bb.
This takes into account how many parallel operations we
can actually do of a given type, and also the latency.
diff --git a/gcc/testsuite/gcc.target/powerpc/pr98519.c b/gcc/testsuite/gcc.target/powerpc/pr98519.c
new file mode 100644
index 00000000000..25918bac3ed
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr98519.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
+
+/* Compile with -mcpu=power10. The lxsd instruction should not be replaced
+ with a plxsd. */
+typedef vector double vf64_t;
+
+static double test_f64[16];
+
+vf64_t
+bug (void)
+{
+ vf64_t j0;
+ __asm__("lxsd%X1 %0,%1;" : "=v" (j0) : "m" (test_f64));
+ return j0;
+}
+
+/* { dg-final { scan-assembler {\mlxsd\M} } } */
+/* { dg-final { scan-assembler-not {\mplxsd\M} } } */
^ permalink raw reply [flat|nested] 4+ messages in thread
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