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* [gcc r12-6994] AArch64: use canonical ordering for complex mul, fma and fms
@ 2022-02-02 10:54 Tamar Christina
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From: Tamar Christina @ 2022-02-02 10:54 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:ab95fe61fea38fbac7f4e00abd32c2530532351a
commit r12-6994-gab95fe61fea38fbac7f4e00abd32c2530532351a
Author: Tamar Christina <tamar.christina@arm.com>
Date: Wed Feb 2 10:51:38 2022 +0000
AArch64: use canonical ordering for complex mul, fma and fms
After the first patch in the series this updates the optabs to expect the
canonical sequence.
gcc/ChangeLog:
PR tree-optimization/102819
PR tree-optimization/103169
* config/aarch64/aarch64-simd.md (cml<fcmac1><conj_op><mode>4): Use
canonical order.
* config/aarch64/aarch64-sve.md (cml<fcmac1><conj_op><mode>4): Likewise.
Diff:
---
gcc/config/aarch64/aarch64-simd.md | 14 +++++++-------
gcc/config/aarch64/aarch64-sve.md | 6 +++---
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 71c429fe75a..13255be84fd 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -556,17 +556,17 @@
;; remainder. Because of this, expand early.
(define_expand "cml<fcmac1><conj_op><mode>4"
[(set (match_operand:VHSDF 0 "register_operand")
- (plus:VHSDF (match_operand:VHSDF 1 "register_operand")
- (unspec:VHSDF [(match_operand:VHSDF 2 "register_operand")
- (match_operand:VHSDF 3 "register_operand")]
- FCMLA_OP)))]
+ (plus:VHSDF (unspec:VHSDF [(match_operand:VHSDF 1 "register_operand")
+ (match_operand:VHSDF 2 "register_operand")]
+ FCMLA_OP)
+ (match_operand:VHSDF 3 "register_operand")))]
"TARGET_COMPLEX && !BYTES_BIG_ENDIAN"
{
rtx tmp = gen_reg_rtx (<MODE>mode);
- emit_insn (gen_aarch64_fcmla<rotsplit1><mode> (tmp, operands[1],
- operands[3], operands[2]));
+ emit_insn (gen_aarch64_fcmla<rotsplit1><mode> (tmp, operands[3],
+ operands[2], operands[1]));
emit_insn (gen_aarch64_fcmla<rotsplit2><mode> (operands[0], tmp,
- operands[3], operands[2]));
+ operands[2], operands[1]));
DONE;
})
diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md
index bd22fe52a31..bd60e65b0c3 100644
--- a/gcc/config/aarch64/aarch64-sve.md
+++ b/gcc/config/aarch64/aarch64-sve.md
@@ -7278,11 +7278,11 @@
rtx tmp = gen_reg_rtx (<MODE>mode);
emit_insn
(gen_aarch64_pred_fcmla<sve_rot1><mode> (tmp, operands[4],
- operands[3], operands[2],
- operands[1], operands[5]));
+ operands[2], operands[1],
+ operands[3], operands[5]));
emit_insn
(gen_aarch64_pred_fcmla<sve_rot2><mode> (operands[0], operands[4],
- operands[3], operands[2],
+ operands[2], operands[1],
tmp, operands[5]));
DONE;
})
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