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* [gcc(refs/users/meissner/heads/work079)] Update ChangeLog.meissner.
@ 2022-03-02 18:12 Michael Meissner
0 siblings, 0 replies; 9+ messages in thread
From: Michael Meissner @ 2022-03-02 18:12 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:5f77ba2d465e85f25fad0405bccbfa1b77d43277
commit 5f77ba2d465e85f25fad0405bccbfa1b77d43277
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue Mar 1 01:37:09 2022 -0500
Update ChangeLog.meissner.
2022-03-01 Michael Meissner <meissner@linux.ibm.com>
gcc/
* ChangeLog.meissner: Update.
Diff:
---
gcc/ChangeLog.meissner | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 4ec0bbcb9fd..16c600b6123 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,8 @@
+work079, patch #2:
+2022-03-01 Michael Meissner <meissner@linux.ibm.com>
+
+ * ChangeLog.meissner: Update.
+
2022-02-28 Michael Meissner <meissner@linux.ibm.com>
Rebase to b6298e5b75a 03418e431cc
@@ -6,6 +11,7 @@
Rebase to b6298e5b75a 03418e431cc
+work079, patch #1:
2022-02-25 Michael Meissner <meissner@linux.ibm.com>
PR target/104698
^ permalink raw reply [flat|nested] 9+ messages in thread
* [gcc(refs/users/meissner/heads/work079)] Update ChangeLog.meissner.
@ 2022-03-03 2:06 Michael Meissner
0 siblings, 0 replies; 9+ messages in thread
From: Michael Meissner @ 2022-03-03 2:06 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:3a2f0251a12712537e36c5e9f93e74b3916739f5
commit 3a2f0251a12712537e36c5e9f93e74b3916739f5
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Mar 2 21:06:34 2022 -0500
Update ChangeLog.meissner.
2022-03-02 Michael Meissner <meissner@linux.ibm.com>
gcc/
* ChangeLog.meissner: Update.
gcc/testsuite/
* ChangeLog.meissner: Update.
Diff:
---
gcc/ChangeLog.meissner | 36 +++++++++++++++++++++++++++---------
gcc/testsuite/ChangeLog.meissner | 18 ++++++++++++++++++
2 files changed, 45 insertions(+), 9 deletions(-)
diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index de81aebfaeb..9e3ba884853 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,14 +1,32 @@
-work079, patch #2:
-2022-03-01 Michael Meissner <meissner@linux.ibm.com>
+work079, patch #4:
+2022-03-02 Michael Meissner <meissner@linux.ibm.com>
PR target/103109
* config/rs6000/rs6000.md (su_int32): New code attribute.
- (<u>mul<mode><dmode>3): Convert into define_insn_and_split.
+ (<u>mul<mode><dmode>3): Convert from define_expand to
+ define_insn_and_split.
(maddld<mode>4): Add generator function.
(<u>mulditi3_<u>adddi3): New insn.
(<u>mulditi3_add_const): New insn.
- (addti3): Convert into define_insn_and_split.
+ (<u>mulditi3_<u>adddi3_upper): New insn.
+ (addti3): Convert from define_expand to define_insn_and_split.
(subti3): Likewise.
+ * config/rs6000/vsx.md (extendditi2): Allow on power9 systems.
+ Add isa attribute for the stuff that needs power10 support.
+ (zero_extendditi2): New insn.
+
+work079, patch #3
+2022-03-02 Michael Meissner <meissner@linux.ibm.com>
+
+ PR target/104698
+ * config/rs6000/vsx.md (mtvsrdd_diti_w1): Delete.
+ (extendditi2): Convert from define_expand to
+ define_insn_and_split. Replace with code to deal with both GPR
+ registers and with altivec registers.
+
+2022-03-02 Michael Meissner <meissner@linux.ibm.com>
+
+ Rebase to 8f1243ed62a 042fc77d5dc
2022-02-28 Michael Meissner <meissner@linux.ibm.com>
@@ -18,13 +36,13 @@ work079, patch #2:
Rebase to b6298e5b75a 03418e431cc
+work079, patch #2:
+
+ Patch reverted.
+
work079, patch #1:
-2022-02-25 Michael Meissner <meissner@linux.ibm.com>
- PR target/104698
- * config/rs6000/vsx.md (mtvsrdd_diti_w1): Delete.
- (extendditi2): Replace with code to deal with both GPR registers
- and with altivec registers.
+ Patch reverted.
2022-02-25 Michael Meissner <meissner@linux.ibm.com>
diff --git a/gcc/testsuite/ChangeLog.meissner b/gcc/testsuite/ChangeLog.meissner
index a7b794405a2..eab3cd7f44a 100644
--- a/gcc/testsuite/ChangeLog.meissner
+++ b/gcc/testsuite/ChangeLog.meissner
@@ -1,3 +1,21 @@
+work079, patch #4:
+2022-03-02 Michael Meissner <meissner@linux.ibm.com>
+
+gcc/testsuite/
+ PR target/103109
+ * gcc.target/powerpc/pr103109.c: New test.
+
+work079, patch #3:
+2022-03-02 Michael Meissner <meissner@linux.ibm.com>
+
+ PR target/104698
+ * gcc.target/powerpc/pr104698-1.c: New test.
+ * gcc.target/powerpc/pr104698-2.c: New test.
+
+2022-03-02 Michael Meissner <meissner@linux.ibm.com>
+
+ Rebase to 8f1243ed62a 042fc77d5dc
+
2022-02-28 Michael Meissner <meissner@linux.ibm.com>
Rebase to b6298e5b75a 03418e431cc
^ permalink raw reply [flat|nested] 9+ messages in thread
* [gcc(refs/users/meissner/heads/work079)] Update ChangeLog.meissner.
@ 2022-03-02 18:13 Michael Meissner
0 siblings, 0 replies; 9+ messages in thread
From: Michael Meissner @ 2022-03-02 18:13 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:1a10e0bc71561d4b4624b7fb9a8d59de49aa3a21
commit 1a10e0bc71561d4b4624b7fb9a8d59de49aa3a21
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue Mar 1 01:39:38 2022 -0500
Update ChangeLog.meissner.
2022-03-01 Michael Meissner <meissner@linux.ibm.com>
gcc/
* ChangeLog.meissner: Update.
Diff:
---
gcc/ChangeLog.meissner | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 16c600b6123..de81aebfaeb 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,7 +1,14 @@
work079, patch #2:
2022-03-01 Michael Meissner <meissner@linux.ibm.com>
- * ChangeLog.meissner: Update.
+ PR target/103109
+ * config/rs6000/rs6000.md (su_int32): New code attribute.
+ (<u>mul<mode><dmode>3): Convert into define_insn_and_split.
+ (maddld<mode>4): Add generator function.
+ (<u>mulditi3_<u>adddi3): New insn.
+ (<u>mulditi3_add_const): New insn.
+ (addti3): Convert into define_insn_and_split.
+ (subti3): Likewise.
2022-02-28 Michael Meissner <meissner@linux.ibm.com>
^ permalink raw reply [flat|nested] 9+ messages in thread
* [gcc(refs/users/meissner/heads/work079)] Update ChangeLog.meissner.
@ 2022-03-02 18:12 Michael Meissner
0 siblings, 0 replies; 9+ messages in thread
From: Michael Meissner @ 2022-03-02 18:12 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:d4a0e5f5a878cdc4c67df09f95a7428279bf8606
commit d4a0e5f5a878cdc4c67df09f95a7428279bf8606
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Feb 25 23:48:29 2022 -0500
Update ChangeLog.meissner.
2022-02-25 Michael Meissner <meissner@linux.ibm.com>
gcc/
* ChangeLog.meissner: Update.
Diff:
---
gcc/ChangeLog.meissner | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index e6cb0f082fb..84c0dfee74c 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,10 @@
+2022-02-25 Michael Meissner <meissner@linux.ibm.com>
+
+ PR target/104698
+ * config/rs6000/vsx.md (mtvsrdd_diti_w1): Delete.
+ (extendditi2): Replace with code to deal with both GPR registers
+ and with altivec registers.
+
2022-02-25 Michael Meissner <meissner@linux.ibm.com>
Rebase to d81cbbdd9a9 98007f77f9f.
^ permalink raw reply [flat|nested] 9+ messages in thread
* [gcc(refs/users/meissner/heads/work079)] Update ChangeLog.meissner.
@ 2022-03-02 18:12 Michael Meissner
0 siblings, 0 replies; 9+ messages in thread
From: Michael Meissner @ 2022-03-02 18:12 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:1299627f271d178355c39bbb3ef30ba340eec05b
commit 1299627f271d178355c39bbb3ef30ba340eec05b
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Feb 25 23:48:29 2022 -0500
Update ChangeLog.meissner.
2022-02-25 Michael Meissner <meissner@linux.ibm.com>
gcc/
* ChangeLog.meissner: Update.
Diff:
---
gcc/ChangeLog.meissner | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index e6cb0f082fb..84c0dfee74c 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,10 @@
+2022-02-25 Michael Meissner <meissner@linux.ibm.com>
+
+ PR target/104698
+ * config/rs6000/vsx.md (mtvsrdd_diti_w1): Delete.
+ (extendditi2): Replace with code to deal with both GPR registers
+ and with altivec registers.
+
2022-02-25 Michael Meissner <meissner@linux.ibm.com>
Rebase to d81cbbdd9a9 98007f77f9f.
^ permalink raw reply [flat|nested] 9+ messages in thread
* [gcc(refs/users/meissner/heads/work079)] Update ChangeLog.meissner.
@ 2022-03-01 6:39 Michael Meissner
0 siblings, 0 replies; 9+ messages in thread
From: Michael Meissner @ 2022-03-01 6:39 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:216649ac16adf12b4762c20c43bf32325d48d283
commit 216649ac16adf12b4762c20c43bf32325d48d283
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue Mar 1 01:39:38 2022 -0500
Update ChangeLog.meissner.
2022-03-01 Michael Meissner <meissner@linux.ibm.com>
gcc/
* ChangeLog.meissner: Update.
Diff:
---
gcc/ChangeLog.meissner | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 16c600b6123..de81aebfaeb 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,7 +1,14 @@
work079, patch #2:
2022-03-01 Michael Meissner <meissner@linux.ibm.com>
- * ChangeLog.meissner: Update.
+ PR target/103109
+ * config/rs6000/rs6000.md (su_int32): New code attribute.
+ (<u>mul<mode><dmode>3): Convert into define_insn_and_split.
+ (maddld<mode>4): Add generator function.
+ (<u>mulditi3_<u>adddi3): New insn.
+ (<u>mulditi3_add_const): New insn.
+ (addti3): Convert into define_insn_and_split.
+ (subti3): Likewise.
2022-02-28 Michael Meissner <meissner@linux.ibm.com>
^ permalink raw reply [flat|nested] 9+ messages in thread
* [gcc(refs/users/meissner/heads/work079)] Update ChangeLog.meissner.
@ 2022-03-01 6:37 Michael Meissner
0 siblings, 0 replies; 9+ messages in thread
From: Michael Meissner @ 2022-03-01 6:37 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:52b04f71de701c955269d78ece39be1953b90da0
commit 52b04f71de701c955269d78ece39be1953b90da0
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue Mar 1 01:37:09 2022 -0500
Update ChangeLog.meissner.
2022-03-01 Michael Meissner <meissner@linux.ibm.com>
gcc/
* ChangeLog.meissner: Update.
Diff:
---
gcc/ChangeLog.meissner | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 4ec0bbcb9fd..16c600b6123 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,8 @@
+work079, patch #2:
+2022-03-01 Michael Meissner <meissner@linux.ibm.com>
+
+ * ChangeLog.meissner: Update.
+
2022-02-28 Michael Meissner <meissner@linux.ibm.com>
Rebase to b6298e5b75a 03418e431cc
@@ -6,6 +11,7 @@
Rebase to b6298e5b75a 03418e431cc
+work079, patch #1:
2022-02-25 Michael Meissner <meissner@linux.ibm.com>
PR target/104698
^ permalink raw reply [flat|nested] 9+ messages in thread
* [gcc(refs/users/meissner/heads/work079)] Update ChangeLog.meissner.
@ 2022-03-01 0:41 Michael Meissner
0 siblings, 0 replies; 9+ messages in thread
From: Michael Meissner @ 2022-03-01 0:41 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:bfd36f1147b18934d53d7e6d7729249dcfdb84f7
commit bfd36f1147b18934d53d7e6d7729249dcfdb84f7
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Feb 25 23:48:29 2022 -0500
Update ChangeLog.meissner.
2022-02-25 Michael Meissner <meissner@linux.ibm.com>
gcc/
* ChangeLog.meissner: Update.
Diff:
---
gcc/ChangeLog.meissner | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index e6cb0f082fb..84c0dfee74c 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,10 @@
+2022-02-25 Michael Meissner <meissner@linux.ibm.com>
+
+ PR target/104698
+ * config/rs6000/vsx.md (mtvsrdd_diti_w1): Delete.
+ (extendditi2): Replace with code to deal with both GPR registers
+ and with altivec registers.
+
2022-02-25 Michael Meissner <meissner@linux.ibm.com>
Rebase to d81cbbdd9a9 98007f77f9f.
^ permalink raw reply [flat|nested] 9+ messages in thread
* [gcc(refs/users/meissner/heads/work079)] Update ChangeLog.meissner.
@ 2022-02-26 4:48 Michael Meissner
0 siblings, 0 replies; 9+ messages in thread
From: Michael Meissner @ 2022-02-26 4:48 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:f10969e87669aebc537bc7cd5e55c4d74281180e
commit f10969e87669aebc537bc7cd5e55c4d74281180e
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Feb 25 23:48:29 2022 -0500
Update ChangeLog.meissner.
2022-02-25 Michael Meissner <meissner@linux.ibm.com>
gcc/
* ChangeLog.meissner: Update.
Diff:
---
gcc/ChangeLog.meissner | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index e6cb0f082fb..84c0dfee74c 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,10 @@
+2022-02-25 Michael Meissner <meissner@linux.ibm.com>
+
+ PR target/104698
+ * config/rs6000/vsx.md (mtvsrdd_diti_w1): Delete.
+ (extendditi2): Replace with code to deal with both GPR registers
+ and with altivec registers.
+
2022-02-25 Michael Meissner <meissner@linux.ibm.com>
Rebase to d81cbbdd9a9 98007f77f9f.
^ permalink raw reply [flat|nested] 9+ messages in thread
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