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* [gcc(refs/users/meissner/heads/work081)] Update ChangeLog.meissner.
@ 2022-03-15 2:16 Michael Meissner
0 siblings, 0 replies; 7+ messages in thread
From: Michael Meissner @ 2022-03-15 2:16 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:09b835a66ebc79f85a0a441dc290bc2c87c438e4
commit 09b835a66ebc79f85a0a441dc290bc2c87c438e4
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Mon Mar 14 22:16:30 2022 -0400
Update ChangeLog.meissner.
2022-03-14 Michael Meissner <meissner@linux.ibm.com>
gcc/
* ChangeLog.meissner: Update.
Diff:
---
gcc/ChangeLog.meissner | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index aee2b2ea722..c929d8339e5 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,30 @@
+========== Work081, patch #8
+Add zero_extendditi2.
+
+2022-03-14 Michael Meissner <meissner@linux.ibm.com>
+
+gcc/
+ * config/rs6000/vsx.md (zero_extendditi2): New insn.
+
+
+========== Work081, patch #7
+Optimize extendditi2 GPR to VSX register.
+
+2022-03-12 Michael Meissner <meissner@linux.ibm.com>
+
+gcc/
+ * config/rs6000/vsx.md (extendditi2): Optimize extendditi2 GPR to
+ VSX register.
+
+========== Work081, patch #6
+Improve extendditi2
+
+2022-03-11 Michael Meissner <meissner@linux.ibm.com>
+
+gcc/
+ * config/rs6000/vsx.md (extendditi2): Improve code for GPR to
+ vector register.
+
========== Work081, patch #5
Allow extendditi2 on power9
^ permalink raw reply [flat|nested] 7+ messages in thread
* [gcc(refs/users/meissner/heads/work081)] Update ChangeLog.meissner.
@ 2022-03-15 21:49 Michael Meissner
0 siblings, 0 replies; 7+ messages in thread
From: Michael Meissner @ 2022-03-15 21:49 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:e705f8c732738a02618c25af38cd09f1dbc79d9e
commit e705f8c732738a02618c25af38cd09f1dbc79d9e
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue Mar 15 17:49:33 2022 -0400
Update ChangeLog.meissner.
2022-03-15 Michael Meissner <meissner@linux.ibm.com>
gcc/
* ChangeLog.meissner: Update.
Diff:
---
gcc/ChangeLog.meissner | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index c929d8339e5..56774bfee83 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,21 +1,23 @@
========== Work081, patch #8
Add zero_extendditi2.
-2022-03-14 Michael Meissner <meissner@linux.ibm.com>
+2022-03-15 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (zero_extendditi2): New insn.
-
========== Work081, patch #7
Optimize extendditi2 GPR to VSX register.
-2022-03-12 Michael Meissner <meissner@linux.ibm.com>
+2022-03-15 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (extendditi2): Optimize extendditi2 GPR to
VSX register.
+gcc/testsuite/
+ * gcc.target/powerpc/pr104698-2.c: Update instruction counts.
+
========== Work081, patch #6
Improve extendditi2
^ permalink raw reply [flat|nested] 7+ messages in thread
* [gcc(refs/users/meissner/heads/work081)] Update ChangeLog.meissner.
@ 2022-03-11 20:13 Michael Meissner
0 siblings, 0 replies; 7+ messages in thread
From: Michael Meissner @ 2022-03-11 20:13 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:f766c8c8d22123da877f96016b93361ba789c755
commit f766c8c8d22123da877f96016b93361ba789c755
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Mar 11 15:12:55 2022 -0500
Update ChangeLog.meissner.
2022-03-11 Michael Meissner <meissner@linux.ibm.com>
gcc/
* ChangeLog.meissner: Update.
Diff:
---
gcc/ChangeLog.meissner | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 4911d732a86..aee2b2ea722 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,13 @@
+========== Work081, patch #5
+Allow extendditi2 on power9
+
+2022-03-11 Michael Meissner <meissner@linux.ibm.com>
+
+gcc/
+ PR target/103109
+ * config/rs6000/vsx.md (extendditi2): Allow extendidti2 to run on
+ a power9 system.
+
========== Work081, patch #4
Fix DImode to TImode sign extend issue
^ permalink raw reply [flat|nested] 7+ messages in thread
* [gcc(refs/users/meissner/heads/work081)] Update ChangeLog.meissner.
@ 2022-03-11 1:44 Michael Meissner
0 siblings, 0 replies; 7+ messages in thread
From: Michael Meissner @ 2022-03-11 1:44 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:bd6771b43e7cf2cd3012c0694c72763dcb0a5f12
commit bd6771b43e7cf2cd3012c0694c72763dcb0a5f12
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Mar 10 20:43:14 2022 -0500
Update ChangeLog.meissner.
2022-03-10 Michael Meissner <meissner@linux.ibm.com>
gcc/
* ChangeLog.meissner: Update.
Diff:
---
gcc/ChangeLog.meissner | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 1c9b6b19bc7..4911d732a86 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,32 @@
+========== Work081, patch #4
+Fix DImode to TImode sign extend issue
+
+PR target/104868 had had an issue where my code that updated the DImode to
+TImode sign extension for power10 failed. In looking at the failure
+message, the reason is when extendditi2 tries to split the insn, it
+generates an insn that does not satisfy its constraints:
+
+ (set (reg:V2DI 65 1)
+ (vec_duplicate:V2DI (reg:DI 0)))
+
+The reason is vsx_splat_v2di does not allow GPR register 0 when the will
+be generating a mtvsrdd instruction. In the definition of the mtvsrdd
+instruction, if the RA register is 0, it means clear the upper 64 bits of
+the vector instead of moving register GPR 0 to those bits.
+
+When I wrote the extendditi2 pattern, I forgot that mtvsrdd had that
+behavior so I used a 'r' constraint instead of 'b'. In the rare case
+where the value is in GPR register 0, this split will fail.
+
+This patch uses the right constraint for extendditi2.
+
+2022-03-10 Michael Meissner <meissner@linux.ibm.com>
+
+gcc/
+ PR target/104868
+ * config/rs6000/vsx.md (extendditi2): Use a 'b' constraint when
+ moving from a GPR register to an Altivec register.
+
========== Work081, patch #3
Make power8-fusion depend only on tuning for power8.
^ permalink raw reply [flat|nested] 7+ messages in thread
* [gcc(refs/users/meissner/heads/work081)] Update ChangeLog.meissner.
@ 2022-03-09 23:08 Michael Meissner
0 siblings, 0 replies; 7+ messages in thread
From: Michael Meissner @ 2022-03-09 23:08 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:0a1c1737ae6fda9686c31d0f53ac917e821ac261
commit 0a1c1737ae6fda9686c31d0f53ac917e821ac261
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Mar 9 18:06:42 2022 -0500
Update ChangeLog.meissner.
2022-03-09 Michael Meissner <meissner@linux.ibm.com>
gcc/
* ChangeLog.meissner: Update.
Diff:
---
gcc/ChangeLog.meissner | 50 ++++++++++++++++++++++++++++++--------------------
1 file changed, 30 insertions(+), 20 deletions(-)
diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 85818ac5b9a..1c9b6b19bc7 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,20 +1,19 @@
-========== Work081, patch #2
+========== Work081, patch #3
-Allow power10/power9 to inline explicit power8 functions
+Make power8-fusion depend only on tuning for power8.
-The power8 fusion support was set automatically when -mcpu=power8 or
--mtune=power8 was used, and it was cleared for other cpu's. However, if
-you used the target attribute or target #pragma to change the default cpu
-type or tuning, you would get an error that a target specifiction option
-mismatch occurred.
+The power8 fusion support used to be set automatically when -mcpu=power8 or
+-mtune=power8 was used, and it was cleared for other cpu's. However, if you
+used the target attribute or target #pragma to change the default cpu type or
+tuning, you would get an error that a target specifiction option mismatch
+occurred.
-This code moves the power8 fusion option and power8 fusion sign option
-support from being option flags to being a separate option variables.
-This means the code in can_inline_p will not complain about an option
-mismatch. If the user did not explicitly set these options, they will be
-set automatically if we are tuning for power8.
+This code removes the -mpower8-fusion and -mpower8-fusion-sign options, and
+only enables power8 fusion if we are tuning for a power8. Power8 sign fusion
+is only enabled if we are tuning for a power8 and we have -O3 option or
+higher.
-2022-03-08 Michael Meissner <meissner@linux.ibm.com>
+2022-03-09 Michael Meissner <meissner@linux.ibm.com>
gcc/
PR target/102059
@@ -22,19 +21,30 @@ gcc/
(ISA_3_0_MASKS_SERVER): Don't clear the fusion masks.
(POWERPC_MASKS): Remove OPTION_MASK_P8_FUSION.
* config/rs6000/rs6000.cc (rs6000_option_override_internal):
- Change how power8 fusion options are set from being an option mask
- to being separate variables.
- (rs6000_opt_masks): Remove -mpower8-fusion and
- -mpower8-fusion-sign.
- * config/rs6000/rs6000.h (MASK_P8_FUSION): Delete.
- * config/rs6000/rs6000.opt (-mpower8-fusion): Change from being an
- option mask to being a separate variable.
+ Delete code that set the power8 fusion options automatically.
+ (rs6000_opt_masks): Allow #pragma target and attribute target to set
+ power8-fusion and power8-fusion-sign, but these no longer represent
+ options that the user can set.
+ (rs6000_print_options_internal): Skip printing nop options.
+ * config/rs6000/rs6000.h (TARGET_P8_FUSION): New macro.
+ (TARGET_P8_FUSION_SIGN): Likewise.
+ (MASK_P8_FUSION): Delete.
+ * config/rs6000/rs6000.opt (-mpower8-fusion): Recognize the option but
+ ignore the no form and warn that the option was removed for the regular
+ form.
(-mpower8-fusion-sign): Likewise.
+ * doc/invoke.texi (RS/6000 and PowerPC Options): Delete -mpower8-fusion
+ and -mpower8-fusion-sign.
gcc/testsuite/
PR target/102059
+ * gcc.dg/lto/pr102059-1_0.c: Remove -mno-power8-fusion.
+ * gcc.dg/lto/pr102059-2_0.c: Likewise.
+ * gcc.target/powerpc/pr102059-3.c: Likewise.
* gcc.target/powerpc/pr102059-4.c: New test.
+========== Work081, patch #2 was reverted
+
========== Work081, patch #1 was reverted.
========== Work081, creation
^ permalink raw reply [flat|nested] 7+ messages in thread
* [gcc(refs/users/meissner/heads/work081)] Update ChangeLog.meissner.
@ 2022-03-09 7:01 Michael Meissner
0 siblings, 0 replies; 7+ messages in thread
From: Michael Meissner @ 2022-03-09 7:01 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:c286b97c254fdcdf72c7f5bbd932e8017883084d
commit c286b97c254fdcdf72c7f5bbd932e8017883084d
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Mar 9 02:00:53 2022 -0500
Update ChangeLog.meissner.
2022-03-08 Michael Meissner <meissner@linux.ibm.com>
gcc/
* ChangeLog.meissner: Update.
Diff:
---
gcc/ChangeLog.meissner | 41 +----------------------------------------
1 file changed, 1 insertion(+), 40 deletions(-)
diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index b5981d3d569..85818ac5b9a 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -35,46 +35,7 @@ gcc/testsuite/
PR target/102059
* gcc.target/powerpc/pr102059-4.c: New test.
-========== Work081, patch #1
-
-Optimize multiply/add of DImode extended to TImode.
-
-On power9 and power10 systems, we have instructions that support doing
-64-bit integers converted to 128-bit integers and producing 128-bit
-results. This patch adds support to generate these instructions.
-
-Previously we had define_expands to handle conversion of the 64-bit extend
-to 128-bit and multiply. This patch changes these define_expands to
-define_insn_and_split and then it provides combiner patterns to generate
-thes multiply/add instructions.
-
-To support using this optimization on power9, we extend the sign extend
-DImode to TImode to also run on power9 (added for PR target/104698).
-
-We add support for doing an unsigned DImode to TImode conversion. We need
-these conversions to exist on power9 so that the combiner can properly
-combine the extend, multiply, and add instructions.
-
-2022-03-08 Michael Meissner <meissner@linux.ibm.com>
-
-gcc/
- PR target/103109
- * config/rs6000/rs6000.md (su_int32): New code attribute.
- (<u>mul<mode><dmode>3): Convert from define_expand to
- define_insn_and_split.
- (maddld<mode>4): Add generator function.
- (<u>mulditi3_<u>adddi3): New insn.
- (<u>mulditi3_add_const): New insn.
- (<u>mulditi3_<u>adddi3_upper): New insn.
- (addti3): Convert from define_expand to define_insn_and_split.
- (subti3): Likewise.
- * config/rs6000/vsx.md (extendditi2): Allow on power9 systems.
- Add isa attribute for the stuff that needs power10 support.
- (zero_extendditi2): New insn.
-
-gcc/testsuite/
- PR target/103109
- * gcc.target/powerpc/pr103109.c: New test.
+========== Work081, patch #1 was reverted.
========== Work081, creation
^ permalink raw reply [flat|nested] 7+ messages in thread
* [gcc(refs/users/meissner/heads/work081)] Update ChangeLog.meissner.
@ 2022-03-09 0:22 Michael Meissner
0 siblings, 0 replies; 7+ messages in thread
From: Michael Meissner @ 2022-03-09 0:22 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:fe0631dc160e0b805bb3cd29f50c645a290c50aa
commit fe0631dc160e0b805bb3cd29f50c645a290c50aa
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue Mar 8 19:21:58 2022 -0500
Update ChangeLog.meissner.
2022-03-08 Michael Meissner <meissner@linux.ibm.com>
gcc/
* ChangeLog.meissner: Update.
Diff:
---
gcc/ChangeLog.meissner | 80 ++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 80 insertions(+)
diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 386789ace5b..b5981d3d569 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,83 @@
+========== Work081, patch #2
+
+Allow power10/power9 to inline explicit power8 functions
+
+The power8 fusion support was set automatically when -mcpu=power8 or
+-mtune=power8 was used, and it was cleared for other cpu's. However, if
+you used the target attribute or target #pragma to change the default cpu
+type or tuning, you would get an error that a target specifiction option
+mismatch occurred.
+
+This code moves the power8 fusion option and power8 fusion sign option
+support from being option flags to being a separate option variables.
+This means the code in can_inline_p will not complain about an option
+mismatch. If the user did not explicitly set these options, they will be
+set automatically if we are tuning for power8.
+
+2022-03-08 Michael Meissner <meissner@linux.ibm.com>
+
+gcc/
+ PR target/102059
+ * config/rs6000/rs6000-cpus.def (OTHER_FUSION_MASKS): Delete.
+ (ISA_3_0_MASKS_SERVER): Don't clear the fusion masks.
+ (POWERPC_MASKS): Remove OPTION_MASK_P8_FUSION.
+ * config/rs6000/rs6000.cc (rs6000_option_override_internal):
+ Change how power8 fusion options are set from being an option mask
+ to being separate variables.
+ (rs6000_opt_masks): Remove -mpower8-fusion and
+ -mpower8-fusion-sign.
+ * config/rs6000/rs6000.h (MASK_P8_FUSION): Delete.
+ * config/rs6000/rs6000.opt (-mpower8-fusion): Change from being an
+ option mask to being a separate variable.
+ (-mpower8-fusion-sign): Likewise.
+
+gcc/testsuite/
+ PR target/102059
+ * gcc.target/powerpc/pr102059-4.c: New test.
+
+========== Work081, patch #1
+
+Optimize multiply/add of DImode extended to TImode.
+
+On power9 and power10 systems, we have instructions that support doing
+64-bit integers converted to 128-bit integers and producing 128-bit
+results. This patch adds support to generate these instructions.
+
+Previously we had define_expands to handle conversion of the 64-bit extend
+to 128-bit and multiply. This patch changes these define_expands to
+define_insn_and_split and then it provides combiner patterns to generate
+thes multiply/add instructions.
+
+To support using this optimization on power9, we extend the sign extend
+DImode to TImode to also run on power9 (added for PR target/104698).
+
+We add support for doing an unsigned DImode to TImode conversion. We need
+these conversions to exist on power9 so that the combiner can properly
+combine the extend, multiply, and add instructions.
+
+2022-03-08 Michael Meissner <meissner@linux.ibm.com>
+
+gcc/
+ PR target/103109
+ * config/rs6000/rs6000.md (su_int32): New code attribute.
+ (<u>mul<mode><dmode>3): Convert from define_expand to
+ define_insn_and_split.
+ (maddld<mode>4): Add generator function.
+ (<u>mulditi3_<u>adddi3): New insn.
+ (<u>mulditi3_add_const): New insn.
+ (<u>mulditi3_<u>adddi3_upper): New insn.
+ (addti3): Convert from define_expand to define_insn_and_split.
+ (subti3): Likewise.
+ * config/rs6000/vsx.md (extendditi2): Allow on power9 systems.
+ Add isa attribute for the stuff that needs power10 support.
+ (zero_extendditi2): New insn.
+
+gcc/testsuite/
+ PR target/103109
+ * gcc.target/powerpc/pr103109.c: New test.
+
+========== Work081, creation
+
2022-03-08 Michael Meissner <meissner@linux.ibm.com>
Clone branch
^ permalink raw reply [flat|nested] 7+ messages in thread
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