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* [gcc(refs/users/meissner/heads/work082)] Revert patch.
@ 2022-03-23 18:58 Michael Meissner
0 siblings, 0 replies; 4+ messages in thread
From: Michael Meissner @ 2022-03-23 18:58 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:2e129f240b0e63abc1283035b50fa39eca40d7a5
commit 2e129f240b0e63abc1283035b50fa39eca40d7a5
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Mar 23 14:58:05 2022 -0400
Revert patch.
2022-03-23 Michael Meissner <meissner@linux.ibm.com>
gcc/
PR target/99392
Revert patch.
* config/rs6000/rs6000.md (vsx_splat_<mode>_reg): Use the correct
insn type attribute. Add "p9v" isa attribute as needed.
* ChangeLog.meissner: Update.
Diff:
---
gcc/ChangeLog.meissner | 16 +---------------
gcc/config/rs6000/vsx.md | 3 +--
2 files changed, 2 insertions(+), 17 deletions(-)
diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index b28bab31f0a..ecaf114495d 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,18 +1,4 @@
-==================== Work082, patch #8:
-Improve vsx_splat_<mode>_reg
-
-In looking at PR target/99293, I noticed that the code in
-vsx_splat_<mode>_reg used "vecmove" as the "type" insn attribute when the
-"mtvsrdd" is generated. It should use "mfvsr". I also added a "p9v" isa
-attribute for that alternative.
-
-2022-03-23 Michael Meissner <meissner@linux.ibm.com>
-
-gcc/
- PR target/99392
- * config/rs6000/rs6000.md (vsx_splat_<mode>_reg): Use the correct
- insn type attribute. Add "p9v" isa attribute as needed.
-
+==================== Work082, patch #8 (reverted):
==================== Work082, patch #7:
Improve vsx_extract_<mode>
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 30bcaf8a3e9..031d2560265 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4573,8 +4573,7 @@
"@
xxpermdi %x0,%x1,%x1,0
mtvsrdd %x0,%1,%1"
- [(set_attr "type" "vecperm,mtvsr")
- (set_attr "isa" "*,p9v")])
+ [(set_attr "type" "vecperm,vecmove")])
(define_insn "vsx_splat_<mode>_mem"
[(set (match_operand:VSX_D 0 "vsx_register_operand" "=wa")
^ permalink raw reply [flat|nested] 4+ messages in thread
* [gcc(refs/users/meissner/heads/work082)] Revert patch.
@ 2022-03-24 1:34 Michael Meissner
0 siblings, 0 replies; 4+ messages in thread
From: Michael Meissner @ 2022-03-24 1:34 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:2f61e4c25937b132841aa3eb6c71d7f4f53b09be
commit 2f61e4c25937b132841aa3eb6c71d7f4f53b09be
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Mar 23 21:33:53 2022 -0400
Revert patch.
2022-03-23 Michael Meissner <meissner@linux.ibm.com>
gcc/
PR target/99392
Revert patch.
* config/rs6000/rs6000.md (vsx_extract_<mode>): Split extracts
that are just a move to being a move insn. Use the correct insn
type for the alternatives.
(insn splitter for vsx_extract_<mode>): Add new splitter.
Diff:
---
gcc/config/rs6000/vsx.md | 32 ++++++++++++++++++--------------
1 file changed, 18 insertions(+), 14 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index a3e6e324d33..75b85409cd8 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3417,7 +3417,23 @@
gcc_assert (VSX_REGNO_P (op1_regno));
if (element == VECTOR_ELEMENT_SCALAR_64BIT)
- return "#";
+ {
+ if (op0_regno == op1_regno)
+ return ASM_COMMENT_START " vec_extract to same register";
+
+ else if (INT_REGNO_P (op0_regno) && TARGET_DIRECT_MOVE
+ && TARGET_POWERPC64)
+ return "mfvsrd %0,%x1";
+
+ else if (FP_REGNO_P (op0_regno) && FP_REGNO_P (op1_regno))
+ return "fmr %0,%1";
+
+ else if (VSX_REGNO_P (op0_regno))
+ return "xxlor %x0,%x1,%x1";
+
+ else
+ gcc_unreachable ();
+ }
else if (element == VECTOR_ELEMENT_MFVSRLD_64BIT && INT_REGNO_P (op0_regno)
&& TARGET_P9_VECTOR && TARGET_POWERPC64 && TARGET_DIRECT_MOVE)
@@ -3435,21 +3451,9 @@
else
gcc_unreachable ();
}
- [(set_attr "type" "vecsimple,vecperm,mfvsr,mfvsr")
+ [(set_attr "type" "veclogical,mfvsr,mfvsr,vecperm")
(set_attr "isa" "*,*,p8v,p9v")])
-;; Convert extracting the element in the upper 64-bit bits to just a move.
-(define_split
- [(set (match_operand:<VS_scalar> 0 "gpc_reg_operand")
- (vec_select:<VS_scalar>
- (match_operand:VSX_D 1 "gpc_reg_operand")
- (parallel [(match_operand:QI 2 "vsx_scalar_64bit")])))]
- "VECTOR_MEM_VSX_P (<MODE>mode) && reload_completed"
- [(set (match_dup 0) (match_dup 3))]
-{
- operands[3] = gen_rtx_REG (<VS_scalar>mode, reg_or_subregno (operands[1]));
-})
-
;; Optimize extracting a single scalar element from memory.
(define_insn_and_split "*vsx_extract_<P:mode>_<VSX_D:mode>_load"
[(set (match_operand:<VS_scalar> 0 "register_operand" "=wa,wr")
^ permalink raw reply [flat|nested] 4+ messages in thread
* [gcc(refs/users/meissner/heads/work082)] Revert patch.
@ 2022-03-23 20:16 Michael Meissner
0 siblings, 0 replies; 4+ messages in thread
From: Michael Meissner @ 2022-03-23 20:16 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:0fe4512fdd3d0a1b7f0cb2d6f1ceebf11fa6a668
commit 0fe4512fdd3d0a1b7f0cb2d6f1ceebf11fa6a668
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Mar 23 16:15:45 2022 -0400
Revert patch.
2022-03-23 Michael Meissner <meissner@linux.ibm.com>
gcc/
PR target/99392
Revert patch.
* config/rs6000/rs6000.md (vsx_extract_<mode>): Split extracts
that are just a move to being a move insn. Use the correct insn
type for the alternatives.
(insn splitter for vsx_extract_<mode>): Add new splitter.
* ChangeLog.meissner: Update.
Diff:
---
gcc/ChangeLog.meissner | 27 +-------------------------
gcc/config/rs6000/vsx.md | 49 +++++++++++++++++++++++++++---------------------
2 files changed, 29 insertions(+), 47 deletions(-)
diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index ecaf114495d..f07d4226576 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,31 +1,6 @@
==================== Work082, patch #8 (reverted):
-==================== Work082, patch #7:
-Improve vsx_extract_<mode>
-
-In looking at PR target/99293, I noticed that the code in
-vsx_extract_<mode> could be improved.
-
-When the element being extracted is the element in the upper 64-bits, we
-should do an insn_split to convert this to a simple move. This would
-allow the post reload passes to eliminate the move completely.
-
-The code was written before we moved to LRA for register allocation and it
-restricted the target register to just traditional floating point
-registers. I have changed this to target any VSX register.
-
-The insn type attribute was incorrect in that it used "mfvsr" instead of
-"vecperm" when a xxpermdi would be generated. Also, when a "mvfsrld"
-would be generated, the type should be "mfvsr".
-
-2022-03-23 Michael Meissner <meissner@linux.ibm.com>
-
-gcc/
- PR target/99392
- * config/rs6000/rs6000.md (vsx_extract_<mode>): Split extracts
- that are just a move to being a move insn. Use the correct insn
- type for the alternatives.
- (insn splitter for vsx_extract_<mode>): Add new splitter.
+==================== Work082, patch #7 (reverted):
==================== Work082, patch #6:
Optimize vec_splats of constant vec_extract for V2DI/V2DF.
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 031d2560265..a1c95c61b2e 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3397,27 +3397,46 @@
;; Optimize cases were we can do a simple or direct move.
;; Or see if we can avoid doing the move at all
+;; There are some unresolved problems with reload that show up if an Altivec
+;; register was picked. Limit the scalar value to FPRs for now.
+
(define_insn "vsx_extract_<mode>"
- [(set (match_operand:<VS_scalar> 0 "gpc_reg_operand" "=wa, wa, r, r")
+ [(set (match_operand:<VS_scalar> 0 "gpc_reg_operand" "=d, d, wr, wr")
(vec_select:<VS_scalar>
- (match_operand:VSX_D 1 "gpc_reg_operand" "wa, wa, wa, wa")
+ (match_operand:VSX_D 1 "gpc_reg_operand" "wa, wa, wa, wa")
(parallel
- [(match_operand:QI 2 "const_0_to_1_operand" "wD, n, wD, n")])))]
+ [(match_operand:QI 2 "const_0_to_1_operand" "wD, n, wD, n")])))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
{
int element = INTVAL (operands[2]);
- int op0_regno = reg_or_subregno (operands[0]);
- int op1_regno = reg_or_subregno (operands[1]);
+ int op0_regno = REGNO (operands[0]);
+ int op1_regno = REGNO (operands[1]);
int fldDM;
gcc_assert (IN_RANGE (element, 0, 1));
gcc_assert (VSX_REGNO_P (op1_regno));
if (element == VECTOR_ELEMENT_SCALAR_64BIT)
- return "#";
+ {
+ if (op0_regno == op1_regno)
+ return ASM_COMMENT_START " vec_extract to same register";
+
+ else if (INT_REGNO_P (op0_regno) && TARGET_DIRECT_MOVE
+ && TARGET_POWERPC64)
+ return "mfvsrd %0,%x1";
- if (INT_REGNO_P (op0_regno) && TARGET_P9_VECTOR && TARGET_POWERPC64
- && TARGET_DIRECT_MOVE)
+ else if (FP_REGNO_P (op0_regno) && FP_REGNO_P (op1_regno))
+ return "fmr %0,%1";
+
+ else if (VSX_REGNO_P (op0_regno))
+ return "xxlor %x0,%x1,%x1";
+
+ else
+ gcc_unreachable ();
+ }
+
+ else if (element == VECTOR_ELEMENT_MFVSRLD_64BIT && INT_REGNO_P (op0_regno)
+ && TARGET_P9_VECTOR && TARGET_POWERPC64 && TARGET_DIRECT_MOVE)
return "mfvsrld %0,%x1";
else if (VSX_REGNO_P (op0_regno))
@@ -3432,21 +3451,9 @@
else
gcc_unreachable ();
}
- [(set_attr "type" "*,vecperm,mfvsr,mfvsr")
+ [(set_attr "type" "veclogical,mfvsr,mfvsr,vecperm")
(set_attr "isa" "*,*,p8v,p9v")])
-;; Convert extracting the element in the upper 64-bit bits to just a move.
-(define_split
- [(set (match_operand:<VS_scalar> 0 "gpc_reg_operand")
- (vec_select:<VS_scalar>
- (match_operand:VSX_D 1 "gpc_reg_operand")
- (parallel [(match_operand:QI 2 "vsx_scalar_64bit")])))]
- "VECTOR_MEM_VSX_P (<MODE>mode) && reload_completed"
- [(set (match_dup 0) (match_dup 3))]
-{
- operands[3] = gen_rtx_REG (<VS_scalar>mode, reg_or_subregno (operands[1]));
-})
-
;; Optimize extracting a single scalar element from memory.
(define_insn_and_split "*vsx_extract_<P:mode>_<VSX_D:mode>_load"
[(set (match_operand:<VS_scalar> 0 "register_operand" "=wa,wr")
^ permalink raw reply [flat|nested] 4+ messages in thread
* [gcc(refs/users/meissner/heads/work082)] Revert patch.
@ 2022-03-22 19:54 Michael Meissner
0 siblings, 0 replies; 4+ messages in thread
From: Michael Meissner @ 2022-03-22 19:54 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:6a897d054ad91d34388561b6d70f0f567f1fe0de
commit 6a897d054ad91d34388561b6d70f0f567f1fe0de
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue Mar 22 15:53:49 2022 -0400
Revert patch.
2022-03-22 Michael Meissner <meissner@linux.ibm.com>
gcc/
Revert patch.
PR target/103109
* config/rs6000/rs6000.md (su_int32): New code attribute.
(<u>mul<mode><dmode>3): Convert from define_expand to
define_insn_and_split.
(maddld<mode>4): Add generator function.
(<u>mulditi3_<u>adddi3): New insn.
(<u>mulditi3_add_const): New insn.
(<u>mulditi3_<u>adddi3_upper): New insn.
gcc/testsuite/
Revert patch.
PR target/103109
* gcc.target/powerpc/pr103109.c: New test.
Diff:
---
gcc/config/rs6000/rs6000.md | 128 ++--------------------------
gcc/testsuite/gcc.target/powerpc/pr103109.c | 62 --------------
2 files changed, 6 insertions(+), 184 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index da7367ee642..a74c48efae7 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -676,9 +676,6 @@
(float "")
(unsigned_float "uns")])
-(define_code_attr su_int32 [(sign_extend "s32bit_cint_operand")
- (zero_extend "c32bit_cint_operand")])
-
; Various instructions that come in SI and DI forms.
; A generic w/d attribute, for things like cmpw/cmpd.
(define_mode_attr wd [(QI "b")
@@ -3202,16 +3199,13 @@
"mulhw<u> %0,%1,%2"
[(set_attr "type" "mul")])
-(define_insn_and_split "<u>mul<mode><dmode>3"
- [(set (match_operand:<DMODE> 0 "gpc_reg_operand" "=&r")
+(define_expand "<u>mul<mode><dmode>3"
+ [(set (match_operand:<DMODE> 0 "gpc_reg_operand")
(mult:<DMODE> (any_extend:<DMODE>
- (match_operand:GPR 1 "gpc_reg_operand" "r"))
+ (match_operand:GPR 1 "gpc_reg_operand"))
(any_extend:<DMODE>
- (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
+ (match_operand:GPR 2 "gpc_reg_operand"))))]
"!(<MODE>mode == SImode && TARGET_POWERPC64)"
- "#"
- "&& 1"
- [(pc)]
{
rtx l = gen_reg_rtx (<MODE>mode);
rtx h = gen_reg_rtx (<MODE>mode);
@@ -3220,10 +3214,9 @@
emit_move_insn (gen_lowpart (<MODE>mode, operands[0]), l);
emit_move_insn (gen_highpart (<MODE>mode, operands[0]), h);
DONE;
-}
- [(set_attr "length" "8")])
+})
-(define_insn "maddld<mode>4"
+(define_insn "*maddld<mode>4"
[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
(plus:GPR (mult:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
(match_operand:GPR 2 "gpc_reg_operand" "r"))
@@ -3232,115 +3225,6 @@
"maddld %0,%1,%2,%3"
[(set_attr "type" "mul")])
-(define_insn_and_split "*<u>mulditi3_<u>adddi3"
- [(set (match_operand:TI 0 "gpc_reg_operand" "=&r")
- (plus:TI
- (mult:TI
- (any_extend:TI (match_operand:DI 1 "gpc_reg_operand" "r"))
- (any_extend:TI (match_operand:DI 2 "gpc_reg_operand" "r")))
- (any_extend:TI (match_operand:DI 3 "gpc_reg_operand" "r"))))]
- "TARGET_MADDLD && TARGET_POWERPC64"
- "#"
- "&& 1"
- [(pc)]
-{
- rtx dest = operands[0];
- rtx dest_hi = gen_highpart (DImode, dest);
- rtx dest_lo = gen_lowpart (DImode, dest);
- rtx op1 = operands[1];
- rtx op2 = operands[2];
- rtx op3 = operands[3];
- rtx tmp_hi, tmp_lo;
-
- if (can_create_pseudo_p ())
- {
- tmp_hi = gen_reg_rtx (DImode);
- tmp_lo = gen_reg_rtx (DImode);
- }
- else
- {
- tmp_hi = dest_hi;
- tmp_lo = dest_lo;
- }
-
- emit_insn (gen_<u>mulditi3_<u>adddi3_upper (tmp_hi, op1, op2, op3));
- emit_insn (gen_maddlddi4 (tmp_lo, op1, op2, op3));
-
- if (can_create_pseudo_p ())
- {
- emit_move_insn (dest_hi, tmp_hi);
- emit_move_insn (dest_lo, tmp_lo);
- }
- DONE;
-}
- [(set_attr "length" "8")])
-
-;; Optimize 128-bit multiply with zero/sign extend and adding a constant. We
-;; force the constant into a register to generate li, maddhd, and maddld,
-;; instead of mulld, mulhd, addic, and addze. We can't combine this pattern
-;; with the pattern that handles registers, since constants don't have a sign
-;; or zero extend around them.
-(define_insn_and_split "*<u>mulditi3_add_const"
- [(set (match_operand:TI 0 "gpc_reg_operand" "=&r")
- (plus:TI
- (mult:TI
- (any_extend:TI (match_operand:DI 1 "gpc_reg_operand" "r"))
- (any_extend:TI (match_operand:DI 2 "gpc_reg_operand" "r")))
- (match_operand 3 "<su_int32>" "r")))]
- "TARGET_MADDLD && TARGET_POWERPC64
-"
- "#"
- "&& 1"
- [(pc)]
-{
- rtx dest = operands[0];
- rtx dest_hi = gen_highpart (DImode, dest);
- rtx dest_lo = gen_lowpart (DImode, dest);
- rtx op1 = operands[1];
- rtx op2 = operands[2];
- rtx op3 = force_reg (DImode, operands[3]);
- rtx tmp_hi, tmp_lo;
-
- if (can_create_pseudo_p ())
- {
- tmp_hi = gen_reg_rtx (DImode);
- tmp_lo = gen_reg_rtx (DImode);
- }
- else
- {
- tmp_hi = dest_hi;
- tmp_lo = dest_lo;
- }
-
- emit_insn (gen_<u>mulditi3_<u>adddi3_upper (tmp_hi, op1, op2, op3));
- emit_insn (gen_maddlddi4 (tmp_lo, op1, op2, op3));
-
- if (can_create_pseudo_p ())
- {
- emit_move_insn (dest_hi, tmp_hi);
- emit_move_insn (dest_lo, tmp_lo);
- }
- DONE;
-}
- [(set_attr "length" "8")
- (set_attr "type" "mul")
- (set_attr "size" "64")])
-
-(define_insn "<u>mulditi3_<u>adddi3_upper"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
- (truncate:DI
- (lshiftrt:TI
- (plus:TI
- (mult:TI
- (any_extend:TI (match_operand:DI 1 "gpc_reg_operand" "r"))
- (any_extend:TI (match_operand:DI 2 "gpc_reg_operand" "r")))
- (any_extend:TI (match_operand:DI 3 "gpc_reg_operand" "r")))
- (const_int 64))))]
- "TARGET_MADDLD && TARGET_POWERPC64"
- "maddhd<u> %0,%1,%2,%3"
- [(set_attr "type" "mul")
- (set_attr "size" "64")])
-
(define_insn "udiv<mode>3"
[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
(udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
diff --git a/gcc/testsuite/gcc.target/powerpc/pr103109.c b/gcc/testsuite/gcc.target/powerpc/pr103109.c
deleted file mode 100644
index 7f67816edda..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/pr103109.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/* { dg-require-effective-target int128 } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-/* This test makes sure that GCC generates the maddhd, maddhdu, and maddld
- power9 instructions when doing some forms of 64-bit integers converted to
- 128-bit integers and used with multiply/add operations. */
-
-__int128_t
-s_mult_add (long long a,
- long long b,
- long long c)
-{
- /* maddhd, maddld. */
- return ((__int128_t)a * (__int128_t)b) + (__int128_t)c;
-}
-
-/* Test 32-bit constants that are loaded into GPRs instead of doing the
- mulld/mulhd and then addic/addime or addc/addze. */
-__int128_t
-s_mult_add_m10 (long long a,
- long long b)
-{
- /* maddhd, maddld. */
- return ((__int128_t)a * (__int128_t)b) - 10;
-}
-
-__int128_t
-s_mult_add_70000 (long long a,
- long long b)
-{
- /* maddhd, maddld. */
- return ((__int128_t)a * (__int128_t)b) + 70000;
-}
-
-__uint128_t
-u_mult_add (unsigned long long a,
- unsigned long long b,
- unsigned long long c)
-{
- /* maddhd, maddld. */
- return ((__uint128_t)a * (__uint128_t)b) + (__uint128_t)c;
-}
-
-__uint128_t
-u_mult_add_0x80000000 (unsigned long long a,
- unsigned long long b)
-{
- /* maddhd, maddld. */
- return ((__uint128_t)a * (__uint128_t)b) + 0x80000000UL;
-}
-
-/* { dg-final { scan-assembler-not {\maddc\M} } } */
-/* { dg-final { scan-assembler-not {\madde\M} } } */
-/* { dg-final { scan-assembler-not {\maddid\M} } } */
-/* { dg-final { scan-assembler-not {\maddme\M} } } */
-/* { dg-final { scan-assembler-not {\maddze\M} } } */
-/* { dg-final { scan-assembler-not {\mmulhd\M} } } */
-/* { dg-final { scan-assembler-not {\mmulld\M} } } */
-/* { dg-final { scan-assembler-times {\mmaddhd\M} 3 } } */
-/* { dg-final { scan-assembler-times {\mmaddld\M} 3 } } */
-
^ permalink raw reply [flat|nested] 4+ messages in thread
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2022-03-23 18:58 [gcc(refs/users/meissner/heads/work082)] Revert patch Michael Meissner
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2022-03-24 1:34 Michael Meissner
2022-03-23 20:16 Michael Meissner
2022-03-22 19:54 Michael Meissner
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