[gcc(refs/users/meissner/heads/work083)] Allow vsx_extract_<mode> to use Altivec registers

[gcc(refs/users/meissner/heads/work083)] Allow vsx_extract_<mode> to use Altivec registers

[Michael Meissner]

https://gcc.gnu.org/g:d3d657d307f541928344cfff2dbf75e7f938c69f

commit d3d657d307f541928344cfff2dbf75e7f938c69f
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Thu Mar 24 17:32:59 2022 -0400

    Allow vsx_extract_<mode> to use Altivec registers
    
    In looking at PR target/99293, I noticed that the vsx_extract_<mode>
    pattern for V2DImode and V2DFmode only allowed traditional floating point
    registers, and it did not allow Altivec registers.  The original code was
    written a few years ago when we used the old register allocator, and
    support for scalar floating point in Altivec registers was just being
    added to GCC.
    
    2022-03-24   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
            PR target/99392
            * config/rs6000/rs6000.md (vsx_extract_<mode>): Allow destination
            to be an Altivec register.

Diff:
---
 gcc/config/rs6000/vsx.md | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 2a23807c2dc..d30fd4f2596 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3397,15 +3397,12 @@
 ;; Optimize cases were we can do a simple or direct move.
 ;; Or see if we can avoid doing the move at all
 
-;; There are some unresolved problems with reload that show up if an Altivec
-;; register was picked.  Limit the scalar value to FPRs for now.
-
 (define_insn "vsx_extract_<mode>"
-  [(set (match_operand:<VS_scalar> 0 "gpc_reg_operand" "=d, d,  wr, wr")
+  [(set (match_operand:<VS_scalar> 0 "gpc_reg_operand" "=wa, wa, wr, wr")
 	(vec_select:<VS_scalar>
-	 (match_operand:VSX_D 1 "gpc_reg_operand"      "wa, wa, wa, wa")
+	 (match_operand:VSX_D 1 "gpc_reg_operand"       "wa, wa, wa, wa")
 	 (parallel
-	  [(match_operand:QI 2 "const_0_to_1_operand"  "wD, n,  wD, n")])))]
+	  [(match_operand:QI 2 "const_0_to_1_operand"   "wD, n,  wD, n")])))]
   "VECTOR_MEM_VSX_P (<MODE>mode)"
 {
   int element = INTVAL (operands[2]);

[gcc(refs/users/meissner/heads/work083)] Allow vsx_extract_<mode> to use Altivec registers

[Michael Meissner]

https://gcc.gnu.org/g:66046ec2e26673fe494e6a3290d46dd74b79af77

commit 66046ec2e26673fe494e6a3290d46dd74b79af77
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Thu Mar 24 15:42:37 2022 -0400

    Allow vsx_extract_<mode> to use Altivec registers
    
    In looking at PR target/99293, I noticed that the vsx_extract_<mode>
    pattern for V2DImode and V2DFmode only allowed traditional floating point
    registers, and it did not allow Altivec registers.  The original code was
    written a few years ago when we used the old register allocator, and
    support for scalar floating point in Altivec registers was just being
    added to GCC.
    
    2022-03-24   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
            PR target/99392
            * config/rs6000/rs6000.md (vsx_extract_<mode>): Allow destination
            to be an Altivec register.

Diff:
---
 gcc/config/rs6000/vsx.md | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index c79d796a513..844cca7c369 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3397,15 +3397,12 @@
 ;; Optimize cases were we can do a simple or direct move.
 ;; Or see if we can avoid doing the move at all
 
-;; There are some unresolved problems with reload that show up if an Altivec
-;; register was picked.  Limit the scalar value to FPRs for now.
-
 (define_insn "vsx_extract_<mode>"
-  [(set (match_operand:<VS_scalar> 0 "gpc_reg_operand" "=d, d,  wr, wr")
+  [(set (match_operand:<VS_scalar> 0 "gpc_reg_operand" "=wa, wa, wr, wr")
 	(vec_select:<VS_scalar>
-	 (match_operand:VSX_D 1 "gpc_reg_operand"      "wa, wa, wa, wa")
+	 (match_operand:VSX_D 1 "gpc_reg_operand"       "wa, wa, wa, wa")
 	 (parallel
-	  [(match_operand:QI 2 "const_0_to_1_operand"  "wD, n,  wD, n")])))]
+	  [(match_operand:QI 2 "const_0_to_1_operand"   "wD, n,  wD, n")])))]
   "VECTOR_MEM_VSX_P (<MODE>mode)"
 {
   int element = INTVAL (operands[2]);