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* [gcc r11-9701] x86: Use Yw constraint on *ssse3_pshufbv8qi3
@ 2022-03-28 13:41 H.J. Lu
  0 siblings, 0 replies; only message in thread
From: H.J. Lu @ 2022-03-28 13:41 UTC (permalink / raw)
  To: gcc-cvs

https://gcc.gnu.org/g:a374915186ecab108c983a84b6afcede680100a4

commit r11-9701-ga374915186ecab108c983a84b6afcede680100a4
Author: H.J. Lu <hjl.tools@gmail.com>
Date:   Sun Mar 27 11:07:39 2022 -0700

    x86: Use Yw constraint on *ssse3_pshufbv8qi3
    
    Since AVX512VL and AVX512BW are required for AVX512 VPSHUFB, replace the
    "Yv" register constraint with the "Yw" register constraint.
    
    gcc/
    
            PR target/105068
            * config/i386/sse.md (*ssse3_pshufbv8qi3): Replace "Yv" with
            "Yw".
    
    (cherry picked from commit 08e69332881f8d28ce8b559ffba1900ae5c0d5ee)

Diff:
---
 gcc/config/i386/sse.md | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 32c2036b3a2..56eb8849f36 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -17133,9 +17133,9 @@
 })
 
 (define_insn_and_split "*ssse3_pshufbv8qi3"
-  [(set (match_operand:V8QI 0 "register_operand" "=y,x,Yv")
-	(unspec:V8QI [(match_operand:V8QI 1 "register_operand" "0,0,Yv")
-		      (match_operand:V8QI 2 "register_mmxmem_operand" "ym,x,Yv")
+  [(set (match_operand:V8QI 0 "register_operand" "=y,x,Yw")
+	(unspec:V8QI [(match_operand:V8QI 1 "register_operand" "0,0,Yw")
+		      (match_operand:V8QI 2 "register_mmxmem_operand" "ym,x,Yw")
 		      (match_operand:V4SI 4 "reg_or_const_vector_operand"
 					  "i,3,3")]
 		     UNSPEC_PSHUFB))


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