[gcc(refs/vendors/ARM/heads/morello)] aarch64: Optimise atomic stores of TI

[gcc(refs/vendors/ARM/heads/morello)] aarch64: Optimise atomic stores of TI

[Matthew Malcomson]

https://gcc.gnu.org/g:e8fe664ab427c2bd31233467f92462c6a46a41b8

commit e8fe664ab427c2bd31233467f92462c6a46a41b8
Author: Richard Sandiford <richard.sandiford@arm.com>
Date:   Mon Apr 25 19:48:37 2022 +0100

    aarch64: Optimise atomic stores of TI
    
    Atomic TI stores must be 16-byte aligned.  This means that,
    on Morello, we can implement them using:
    
            st...   czr, [base]
    
    This should be better even for normal-base addresses.  However,
    for alternative-base addresses it has the additional benefit
    of avoiding an out-of-line function, since there are no
    alternative-base forms of the atomic pair instructions that
    TI operations normally use.

Diff:
---
 gcc/config/aarch64/aarch64.c                       |  2 +
 gcc/config/aarch64/atomics.md                      | 15 +++++++
 .../morello/normal-base-sync-lock-release-1.c      | 50 ++++++++++++++++++++++
 3 files changed, 67 insertions(+)

diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 4afa004ec1c..5c31ffc52b4 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -20867,6 +20867,8 @@ aarch64_expand_compare_and_swap (rtx operands[])
       else
 	emit_move_insn (rval, gen_lowpart (r_mode, oldval));
 
+      if (mode == TImode)
+	newval = force_reg (mode, newval);
       emit_insn (gen_aarch64_compare_and_swap_lse (mode, rval, mem,
 						   newval, mod_s));
       cc_reg = aarch64_gen_compare_reg_maybe_ze (NE, drop_capability (rval),
diff --git a/gcc/config/aarch64/atomics.md b/gcc/config/aarch64/atomics.md
index 79e48cd9f64..4e1646e2791 100644
--- a/gcc/config/aarch64/atomics.md
+++ b/gcc/config/aarch64/atomics.md
@@ -942,6 +942,21 @@
   }
 )
 
+(define_expand "atomic_storeti"
+  [(set (match_operand:TI 0 "aarch64_rcpc_memory_operand")
+	(unspec_volatile:TI
+	  [(match_operand:TI 1 "const0_operand")
+	   (match_operand:SI 2 "const_int_operand")]		;; model
+	  UNSPECV_STL))]
+  "TARGET_MORELLO"
+  {
+    operands[0] = adjust_address (operands[0], CADImode, 0);
+    emit_insn (gen_atomic_storecadi (operands[0], CONST0_RTX (CADImode),
+				     operands[2]));
+    DONE;
+  }
+)
+
 (define_insn "atomic_store<mode>"
   [(set (match_operand:ALLIC 0 "aarch64_rcpc_memory_operand" "=Q,Ust")
     (unspec_volatile:ALLIC
diff --git a/gcc/testsuite/gcc.target/aarch64/morello/normal-base-sync-lock-release-1.c b/gcc/testsuite/gcc.target/aarch64/morello/normal-base-sync-lock-release-1.c
new file mode 100644
index 00000000000..38122ac35d8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/morello/normal-base-sync-lock-release-1.c
@@ -0,0 +1,50 @@
+/* { dg-do assemble } */
+/* { dg-additional-options "-foptimize-sibling-calls -save-temps" } */
+/* { dg-final { check-function-bodies "**" ""  { {-O[123s]} } } } */
+/* { dg-skip-if "" { *-*-* } { "-mfake-capability" } { "" } }  */
+
+#include <stdint.h>
+
+typedef __uint128_t uint128;
+
+#define TEST_SIZE(TYPE)			\
+  void					\
+  test_##TYPE (TYPE *ptr)		\
+  {					\
+    __sync_lock_release (ptr);		\
+  }
+
+/*
+** test_uint8_t:
+**	stlrb	wzr, \[[xc]0\]
+**	ret
+*/
+TEST_SIZE (uint8_t)
+
+/*
+** test_uint16_t:
+**	stlrh	wzr, \[[xc]0\]
+**	ret
+*/
+TEST_SIZE (uint16_t)
+
+/*
+** test_uint32_t:
+**	stlr	wzr, \[[xc]0\]
+**	ret
+*/
+TEST_SIZE (uint32_t)
+
+/*
+** test_uint64_t:
+**	stlr	xzr, \[[xc]0\]
+**	ret
+*/
+TEST_SIZE (uint64_t)
+
+/*
+** test_uint128:
+**	stlr	czr, \[[xc]0\]
+**	ret
+*/
+TEST_SIZE (uint128)