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* [gcc r13-283] rs6000: Fix constraint v with rs6000_constraints[RS6000_CONSTRAINT_v]
@ 2022-05-11  7:22 Kewen Lin
  0 siblings, 0 replies; only message in thread
From: Kewen Lin @ 2022-05-11  7:22 UTC (permalink / raw)
  To: gcc-cvs

https://gcc.gnu.org/g:55aa130ef112c6f2c8ef85c218455464c6b29d60

commit r13-283-g55aa130ef112c6f2c8ef85c218455464c6b29d60
Author: Kewen Lin <linkw@linux.ibm.com>
Date:   Wed May 11 01:18:30 2022 -0500

    rs6000: Fix constraint v with rs6000_constraints[RS6000_CONSTRAINT_v]
    
    Currently we hardcode ALTIVEC_REGS for register constraint v and
    RS6000_CONSTRAINT_v looks confusing, this is to fix it with
    rs6000_constraints[RS6000_CONSTRAINT_v] to align with some other
    existing register constraints with RS6000_CONSTRAINT_*.
    
    gcc/ChangeLog:
    
            * config/rs6000/constraints.md (register constraint v): Use
            rs6000_constraints[RS6000_CONSTRAINT_v] instead of ALTIVEC_REGS.

Diff:
---
 gcc/config/rs6000/constraints.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index 7aaffd9f9a8..b361893e289 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -37,7 +37,7 @@
    historically @code{f} was for single-precision and @code{d} was for
    double-precision floating point.")
 
-(define_register_constraint "v" "ALTIVEC_REGS"
+(define_register_constraint "v" "rs6000_constraints[RS6000_CONSTRAINT_v]"
   "An Altivec vector register (VR), @code{v0}@dots{}@code{v31}.")
 
 (define_register_constraint "wa" "rs6000_constraints[RS6000_CONSTRAINT_wa]"


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