[gcc(refs/users/meissner/heads/work089)] Update ChangeLog.meissner.

[Michael Meissner <meissner@gcc.gnu.org>]

https://gcc.gnu.org/g:096bd8ff2b196415b4a61303ca474d7c7eb8e939

commit 096bd8ff2b196415b4a61303ca474d7c7eb8e939
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Thu May 12 18:46:59 2022 -0400

    Update ChangeLog.meissner.
    
    2022-05-12   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
            * ChangeLog.meissner: Update.

Diff:
---
 gcc/ChangeLog.meissner | 69 ++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 69 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 0e1adbcaee4..acc5d7be01c 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,72 @@
+==================== work089 patch #6
+
+Optimize multiply/add of DImode extended to TImode, PR target/103109.
+
+On power9 and power10 systems, we have instructions that support doing
+64-bit integers converted to 128-bit integers and producing 128-bit
+results.  This patch adds support to generate these instructions.
+
+Previously GCC had define_expands to handle conversion of the 64-bit
+extend to 128-bit and multiply.  This patch changes these define_expands
+to define_insn_and_split and then it provides combiner patterns to
+generate thes multiply/add instructions.
+
+To support using this optimization on power9, this patch extend the sign
+extend DImode to TImode to also run on power9 (added for PR
+target/104698).
+
+This patch needs the previous patch to add unsigned DImode to TImode
+conversion so that the combiner can combine the extend, multiply, and add
+instructions.
+
+
+2022-05-12   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+	PR target/103109
+	* config/rs6000/rs6000.md (su_int32): New code attribute.
+	(<u>mul<mode><dmode>3): Convert from define_expand to
+	define_insn_and_split.
+	(maddld<mode>4): Add generator function.
+	(<u>mulditi3_<u>adddi3): New insn.
+	(<u>mulditi3_add_const): New insn.
+	(<u>mulditi3_<u>adddi3_upper): New insn.
+
+gcc/testsuite/
+	PR target/103109
+	* gcc.target/powerpc/pr103109.c: New test.
+
+==================== work089 patch #5
+
+Add zero_extendditi2.  Improve lxvr*x code generation.
+
+This pattern adds zero_extendditi2 so that if we are extending DImode to
+TImode, and we want the result in a vector register, the compiler can
+generate MTVSRDDD.
+
+In addition the patterns for generating lxvr{b,h,w,d}x were tuned to allow
+loading to gpr registers.  This prevents needlessly doing direct moves to
+get the value into the vector registers if the gpr register was already
+selected.
+
+In updating the insn counts for two tests due to these changes, I noticed
+the tests were done at -O0.  I changed this so that the tests are now done
+at the normal -O2 optimization level.
+
+2022-05-012   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+	* config/rs6000/vsx.md (vsx_lxvr<wd>x): Add support for loading to
+	GPR registers.
+	(vsx_stxvr<wd>x): Add support for storing from GPR registers.
+	(zero_extendditi2): New insn.
+
+gcc/testsuite/
+	* gcc.target/powerpc/vsx-load-element-extend-int.c: Use -O2
+	instead of -O0 and update insn counts.
+	* gcc.target/powerpc/vsx-load-element-extend-short.c: Likewise.
+	* gcc.target/powerpc/zero-extend-di-ti.c: New test.
+
 ==================== work089 patch #4
 
 Delay splitting addti3/subti3 until first split pass.