[gcc(refs/users/meissner/heads/dmf003)] Update ChangeLog.meissner.

[gcc(refs/users/meissner/heads/dmf003)] Update ChangeLog.meissner.

[Michael Meissner]

https://gcc.gnu.org/g:52897724ae56ea5ac7c0d61a83d2eb5242ac7d2b

commit 52897724ae56ea5ac7c0d61a83d2eb5242ac7d2b
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Sat Nov 5 00:23:24 2022 -0400

    Update ChangeLog.meissner.
    
    2022-11-04   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * ChangeLog.meissner: Update.

Diff:
---
 gcc/ChangeLog.meissner | 53 ++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 53 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 668e877c883..ccf16fb68c7 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,56 @@
+==================== Dmf003 branch, patch #15.
+
+Add support for 1,024 bit DMR registers.
+
+2022-11-05   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/mma.md (UNSPEC_DM_INSERT512_UPPER): New unspec.
+	(UNSPEC_DM_INSERT512_LOWER): Likewise.
+	(UNSPEC_DM_EXTRACT512): Likewise.
+	(UNSPEC_DMR_RELOAD_FROM_MEMORY): Likewise.
+	(UNSPEC_DMR_RELOAD_TO_MEMORY): Likewise.
+	(movtdo): New define_expand and define_insn_and_split to implement 1,024
+	bit DMR registers.
+	(movtdo_insert512_upper): New insn.
+	(movtdo_insert512_lower): Likewise.
+	(movtdo_extract512): Likewise.
+	(reload_dmr_from_memory): Likewise.
+	(reload_dmr_to_memory): Likewise.
+	* config/rs6000/rs6000-builtin.cc (rs6000_type_string): Add DMR
+	support.
+	(rs6000_init_builtins): Add support for __dmr keyword.
+	* config/rs6000/rs6000-call.cc (rs6000_return_in_memory): Add support
+	for TDOmode.
+	(rs6000_function_arg): Likewise.
+	* config/rs6000/rs6000-modes.def (TDOmode): New mode.
+	* config/rs6000/rs6000.cc (rs6000_hard_regno_nregs_internal): Add
+	support for TDOmode.
+	(rs6000_hard_regno_mode_ok_uncached): Likewise.
+	(rs6000_hard_regno_mode_ok): Likewise.
+	(rs6000_modes_tieable_p): Likewise.
+	(rs6000_debug_reg_global): Likewise.
+	(rs6000_setup_reg_addr_masks): Likewise.
+	(rs6000_init_hard_regno_mode_ok): Add support for TDOmode.  Setup reload
+	hooks for DMR mode.
+	(reg_offset_addressing_ok_p): Add support for TDOmode.
+	(rs6000_emit_move): Likewise.
+	(rs6000_secondary_reload_simple_move): Likewise.
+	(rs6000_secondary_reload_class): Likewise.
+	(rs6000_mangle_type): Add mangling for __dmr type.
+	(rs6000_dmr_register_move_cost): Add support for TDOmode.
+	(rs6000_split_multireg_move): Likewise.
+	(rs6000_invalid_conversion): Likewise.
+	* config/rs6000/rs6000.h (VECTOR_ALIGNMENT_P): Add TDOmode.
+	(enum rs6000_builtin_type_index): Add DMR type nodes.
+	(dmr_type_node): Likewise.
+	(ptr_dmr_type_node): Likewise.
+
+gcc/testsuite/
+
+	* gcc.target/powerpc/dm-1024bit.c: New test.
+
 ==================== Dmf003 branch, patch #14.
 
 Switch to dense math names for all MMA operations.

[gcc(refs/users/meissner/heads/dmf003)] Update ChangeLog.meissner.

[Michael Meissner]

https://gcc.gnu.org/g:1a1231bb10667840d9eb3393d5d4d07d6b31dadb

commit 1a1231bb10667840d9eb3393d5d4d07d6b31dadb
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Wed Nov 9 00:33:56 2022 -0500

    Update ChangeLog.meissner.
    
    2022-11-09   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * ChangeLog.meissner: Update.

Diff:
---
 gcc/ChangeLog.meissner | 327 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 327 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 72065f8fec4..1881974236d 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,330 @@
+==================== Dmf003 branch, patch #23.
+
+Patch libgcc to always use _Float128 and _Complex _Float128 on PowerPC.
+
+2022-11-09   Michael Meissner  <meissner@linux.ibm.com>
+
+libgcc/
+
+	* config/rs6000/quad-float128.h (TF): Delete definition.
+	(TFtype): Define to be _Float128.
+	(TCtype): Change to be _Complex _Float128.
+	* libgcc2.h (TFtype): Allow MD code to override definition.
+	(TCtype): Likewise.
+	* soft-fp/quad.h (TFtype): Likewise.
+
+==================== Dmf003 branch, patch #22.
+
+Update float 128-bit conversions, PR target/107299.
+
+This patch fixes two tests that are still failing when long double is IEEE
+128-bit after the previous 2 patches for PR target/107299 have been applied.
+The tests are:
+
+	gcc.target/powerpc/convert-fp-128.c
+	gcc.target/powerpc/pr85657-3.c
+
+This patch is a rewrite of the patch submitted on August 18th:
+
+| https://gcc.gnu.org/pipermail/gcc-patches/2022-August/599988.html
+
+This patch reworks the conversions between 128-bit binary floating point types.
+Previously, we would call rs6000_expand_float128_convert to do all conversions.
+Now, we only define the conversions between the same representation that turn
+into a NOP.  The appropriate extend or truncate insn is generated, and after
+register allocation, it is converted to a move.
+
+This patch also fixes two places where we want to override the external name
+for the conversion function, and the wrong optab was used.  Previously,
+rs6000_expand_float128_convert would handle the move or generate the call as
+needed.  Now, it lets the machine independent code generate the call.  But if
+we use the machine independent code to generate the call, we need to update the
+name for two optabs where a truncate would be used in terms of converting
+between the modes.  This patch updates those two optabs.
+
+I tested this patch on:
+
+    1)	LE Power10 using --with-cpu=power10 --with-long-double-format=ieee
+    2)	LE Power10 using --with-cpu=power10 --with-long-double-format=ibm
+    3)	LE Power9  using --with-cpu=power9  --with-long-double-format=ibm
+    4)	BE Power8  using --with-cpu=power8  --with-long-double-format=ibm
+
+In the past I have also tested this exact patch on the following systems:
+
+    1)	LE Power10 using --with-cpu=power9  --with-long-double-format=ibm
+    2)	LE Power10 using --with-cpu=power8  --with-long-double-format=ibm
+    3)	LE Power10 using --with-cpu=power10 --with-long-double-format=ibm
+
+There were no regressions in the bootstrap process or running the tests (after
+applying all 3 patches for PR target/107299).  Can I check this patch into the
+trunk?
+
+2022-11-09   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	PR target/107299
+	* config/rs6000/rs6000.cc (init_float128_ieee): Use the correct
+	float_extend or float_truncate optab based on how the machine converts
+	between IEEE 128-bit and IBM 128-bit.
+	* config/rs6000/rs6000.md (IFKF): Delete.
+	(IFKF_reg): Delete.
+	(extendiftf2): Rewrite to be a move if IFmode and TFmode are both IBM
+	128-bit.  Do not run if TFmode is IEEE 128-bit.
+	(extendifkf2): Delete.
+	(extendtfkf2): Delete.
+	(extendtfif2): Delete.
+	(trunciftf2): Delete.
+	(truncifkf2): Delete.
+	(trunckftf2): Delete.
+	(extendkftf2): Implement conversion of IEEE 128-bit types as a move.
+	(trunctfif2): Delete.
+	(trunctfkf2): Implement conversion of IEEE 128-bit types as a move.
+	(extend<mode>tf2_internal): Delete.
+	(extendtf<mode>2_internal): Delete.
+
+==================== Dmf003 branch, patch #21.
+
+Make __float128 use the _Float128 type, PR target/107299.
+
+This patch fixes the issue that GCC cannot build when the default long double
+is IEEE 128-bit.  It fails in building libgcc, specifically when it is trying
+to buld the __mulkc3 function in libgcc.  It is failing in gimple-range-fold.cc
+during the evrp pass.  Ultimately it is failing because the code declared the
+type to use TFmode but it used F128 functions (i.e. KFmode).
+
+	typedef float TFtype __attribute__((mode (TF)));
+	typedef __complex float TCtype __attribute__((mode (TC)));
+
+	TCtype
+	__mulkc3_sw (TFtype a, TFtype b, TFtype c, TFtype d)
+	{
+	  TFtype ac, bd, ad, bc, x, y;
+	  TCtype res;
+
+	  ac = a * c;
+	  bd = b * d;
+	  ad = a * d;
+	  bc = b * c;
+
+	  x = ac - bd;
+	  y = ad + bc;
+
+	  if (__builtin_isnan (x) && __builtin_isnan (y))
+	    {
+	      _Bool recalc = 0;
+	      if (__builtin_isinf (a) || __builtin_isinf (b))
+		{
+
+		  a = __builtin_copysignf128 (__builtin_isinf (a) ? 1 : 0, a);
+		  b = __builtin_copysignf128 (__builtin_isinf (b) ? 1 : 0, b);
+		  if (__builtin_isnan (c))
+		    c = __builtin_copysignf128 (0, c);
+		  if (__builtin_isnan (d))
+		    d = __builtin_copysignf128 (0, d);
+		  recalc = 1;
+		}
+	      if (__builtin_isinf (c) || __builtin_isinf (d))
+		{
+
+		  c = __builtin_copysignf128 (__builtin_isinf (c) ? 1 : 0, c);
+		  d = __builtin_copysignf128 (__builtin_isinf (d) ? 1 : 0, d);
+		  if (__builtin_isnan (a))
+		    a = __builtin_copysignf128 (0, a);
+		  if (__builtin_isnan (b))
+		    b = __builtin_copysignf128 (0, b);
+		  recalc = 1;
+		}
+	      if (!recalc
+		  && (__builtin_isinf (ac) || __builtin_isinf (bd)
+		      || __builtin_isinf (ad) || __builtin_isinf (bc)))
+		{
+
+		  if (__builtin_isnan (a))
+		    a = __builtin_copysignf128 (0, a);
+		  if (__builtin_isnan (b))
+		    b = __builtin_copysignf128 (0, b);
+		  if (__builtin_isnan (c))
+		    c = __builtin_copysignf128 (0, c);
+		  if (__builtin_isnan (d))
+		    d = __builtin_copysignf128 (0, d);
+		  recalc = 1;
+		}
+	      if (recalc)
+		{
+		  x = __builtin_inff128 () * (a * c - b * d);
+		  y = __builtin_inff128 () * (a * d + b * c);
+		}
+	    }
+
+	  __real__ res = x;
+	  __imag__ res = y;
+	  return res;
+	}
+
+Currently GCC uses the long double type node for __float128 if long double is
+IEEE 128-bit.  It did not use the node for _Float128.
+
+Originally this was noticed if you call the nansq function to make a signaling
+NaN (nansq is mapped to nansf128).  Because the type node for _Float128 is
+different from __float128, the machine independent code converts signaling NaNs
+to quiet NaNs if the types are not compatible.  The following tests used to
+fail when run on a system where long double is IEEE 128-bit:
+
+	gcc.dg/torture/float128-nan.c
+	gcc.target/powerpc/nan128-1.c
+
+This patch makes both __float128 and _Float128 use the same type node.
+
+One side effect of not using the long double type node for __float128 is that we
+must only use KFmode for _Float128/__float128.  The libstdc++ library won't
+build if we use TFmode for _Float128 and __float128 when long double is IEEE
+128-bit.
+
+Another minor side effect is that the f128 round to odd fused multiply-add
+function will not merge negatition with the FMA operation when the type is long
+double.  If the type is __float128 or _Float128, then it will continue to do the
+optimization.  The round to odd functions are defined in terms of __float128
+arguments.  For example:
+
+	long double
+	do_fms (long double a, long double b, long double c)
+	{
+	    return __builtin_fmaf128_round_to_odd (a, b, -c);
+	}
+
+will generate (assuming -mabi=ieeelongdouble):
+
+	xsnegqp 4,4
+	xsmaddqpo 4,2,3
+	xxlor 34,36,36
+
+while:
+
+	__float128
+	do_fms (__float128 a, __float128 b, __float128 c)
+	{
+	    return __builtin_fmaf128_round_to_odd (a, b, -c);
+	}
+
+will generate:
+
+	xsmsubqpo 4,2,3
+	xxlor 34,36,36
+
+I tested all 3 patchs for PR target/107299 on:
+
+    1)	LE Power10 using --with-cpu=power10 --with-long-double-format=ieee
+    2)	LE Power10 using --with-cpu=power10 --with-long-double-format=ibm
+    3)	LE Power9  using --with-cpu=power9  --with-long-double-format=ibm
+    4)	BE Power8  using --with-cpu=power8  --with-long-double-format=ibm
+
+Once all 3 patches have been applied, we can once again build GCC when long
+double is IEEE 128-bit.  There were no other regressions with these patches.
+Can I check these patches into the trunk?
+
+2022-11-09   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	PR target/107299
+	* config/rs6000/rs6000-builtin.cc (rs6000_init_builtins): Always use the
+	_Float128 type for __float128.
+	(rs6000_expand_builtin): Only change a KFmode built-in to TFmode, if the
+	built-in passes or returns TFmode.  If the predicate failed because the
+	modes were different, use convert_move to load up the value instead of
+	copy_to_mode_reg.
+	* config/rs6000/rs6000.cc (rs6000_translate_mode_attribute): Don't
+	translate IEEE 128-bit floating point modes to explicit IEEE 128-bit
+	modes (KFmode or KCmode), even if long double is IEEE 128-bit.
+	(rs6000_libgcc_floating_mode_supported_p): Support KFmode all of the
+	time if we support IEEE 128-bit floating point.
+	(rs6000_floatn_mode): _Float128 and _Float128x always uses KFmode.
+
+gcc/testsuite/
+
+	PR target/107299
+	* gcc.target/powerpc/float128-hw12.c: New test.
+	* gcc.target/powerpc/float128-hw13.c: Likewise.
+	* gcc.target/powerpc/float128-hw4.c: Update insns.
+
+==================== Dmf003 branch, patch #20.
+
+Rework 128-bit complex multiply and divide.
+
+This function reworks how the complex multiply and divide built-in functions are
+done.  Previously we created built-in declarations for doing long double complex
+multiply and divide when long double is IEEE 128-bit.  The old code also did not
+support __ibm128 complex multiply and divide if long double is IEEE 128-bit.
+
+In terms of history, I wrote the original code just as I was starting to test
+GCC on systems where IEEE 128-bit long double was the default.  At the time, we
+had not yet started mangling the built-in function names as a way to bridge
+going from a system with 128-bit IBM long double to 128-bin IEEE long double.
+
+The original code depends on there only being two 128-bit types invovled.  With
+the next patch in this series, this assumption will no longer be true.  When
+long double is IEEE 128-bit, there will be 2 IEEE 128-bit types (one for the
+explicit __float128/_Float128 type and one for long double).
+
+The problem is we cannot create two separate built-in functions that resolve to
+the same name.  This is a requirement of add_builtin_function and the C front
+end.  That means for the 3 possible modes (IFmode, KFmode, and TFmode), you can
+only use 2 of them.
+
+This code does not create the built-in declaration with the changed name.
+Instead, it uses the TARGET_MANGLE_DECL_ASSEMBLER_NAME hook to change the name
+before it is written out to the assembler file like it now does for all of the
+other long double built-in functions.
+
+We need to disable using this mapping when we are building libgcc, specifically
+when it is building the floating point 128-bit multiply and divide functions.
+The flag that is used when libgcc is built (-fbuilding-libcc) is only available
+in the C/C++ front ends.  We need to remember that we are building libgcc in the
+rs6000-c.cc support to be able to use this later to decided whether to mangle
+the decl assembler name or not.
+
+When I wrote these patches, I discovered that __ibm128 complex multiply and
+divide had originally not been supported if long double is IEEE 128-bit as it
+would generate calls to __mulic3 and __divic3.  I added tests in the testsuite
+to verify that the correct name (i.e. __multc3 and __divtc3) is used in this
+case.
+
+I tested all 3 patchs for PR target/107299 on:
+
+    1)	LE Power10 using --with-cpu=power10 --with-long-double-format=ieee
+    2)	LE Power10 using --with-cpu=power10 --with-long-double-format=ibm
+    3)	LE Power9  using --with-cpu=power9  --with-long-double-format=ibm
+    4)	BE Power8  using --with-cpu=power8  --with-long-double-format=ibm
+
+Once all 3 patches have been applied, we can once again build GCC when long
+double is IEEE 128-bit.  There were no other regressions with these patches.
+Can I check these patches into the trunk?
+
+2022-11-09   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	PR target/107299
+	* config/rs6000/rs6000-c.cc (rs6000_cpu_cpp_builtins): Set
+	building_libgcc.
+	* config/rs6000/rs6000.cc (create_complex_muldiv): Delete.
+	(init_float128_ieee): Delete code to switch complex multiply and divide
+	for long double.
+	(complex_multiply_builtin_code): New helper function.
+	(complex_divide_builtin_code): Likewise.
+	(rs6000_mangle_decl_assembler_name): Add support for mangling the name
+	of complex 128-bit multiply and divide built-in functions.
+	* config/rs6000/rs6000.opt (building_libgcc): New target variable.
+
+gcc/testsuite/
+
+	PR target/107299
+	* gcc.target/powerpc/divic3-1.c: New test.
+	* gcc.target/powerpc/divic3-2.c: Likewise.
+	* gcc.target/powerpc/mulic3-1.c: Likewise.
+	* gcc.target/powerpc/mulic3-2.c: Likewise.
+
 ==================== Dmf003 branch, patch #17.
 
 Turn off CCP when testing __dmr.

[gcc(refs/users/meissner/heads/dmf003)] Update ChangeLog.meissner.

[Michael Meissner]

https://gcc.gnu.org/g:8a27ebb2c6419a371f366d77d0ed6c7c126c8b1c

commit 8a27ebb2c6419a371f366d77d0ed6c7c126c8b1c
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Wed Nov 9 00:01:53 2022 -0500

    Update ChangeLog.meissner.
    
    2022-11-09   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * ChangeLog.meissner: Update.

Diff:
---
 gcc/ChangeLog.meissner | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 64296fff8aa..72065f8fec4 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,14 @@
+==================== Dmf003 branch, patch #17.
+
+Turn off CCP when testing __dmr.
+
+2022-11-09   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/testsuite/
+
+	* gcc.target/powerpc/dm-1024bit.c: Add -fno-tree-ccp until CCP can
+	handle OPAQUE types.
+
 ==================== Dmf003 branch, patch #16.
 
 Fix spacing.

[gcc(refs/users/meissner/heads/dmf003)] Update ChangeLog.meissner.

[Michael Meissner]

https://gcc.gnu.org/g:414a401782e81dbecb011caeb716547064e33c17

commit 414a401782e81dbecb011caeb716547064e33c17
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Tue Nov 8 11:04:15 2022 -0500

    Update ChangeLog.meissner.
    
    2022-11-08   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * ChangeLog.meissner: Update.

Diff:
---
 gcc/ChangeLog.meissner | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index ccf16fb68c7..64296fff8aa 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,14 @@
+==================== Dmf003 branch, patch #16.
+
+Fix spacing.
+
+2022-11-08   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/rs6000.cc (rs6000_split_multireg_move): Fix spacing
+	issue.
+
 ==================== Dmf003 branch, patch #15.
 
 Add support for 1,024 bit DMR registers.

[gcc(refs/users/meissner/heads/dmf003)] Update ChangeLog.meissner.

[Michael Meissner]

https://gcc.gnu.org/g:330e5128654bd176c5be3999b6197edfec31a357

commit 330e5128654bd176c5be3999b6197edfec31a357
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Nov 4 23:26:39 2022 -0400

    Update ChangeLog.meissner.
    
    2022-11-04   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * ChangeLog.meissner: Update.

Diff:
---
 gcc/ChangeLog.meissner | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index bb8c5c1749e..668e877c883 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -32,6 +32,12 @@ gcc/
 	(mma_<vvi4i4i4>): Likewise.
 	(mma_<avvi4i4i4>): Likewise.
 
+gcc/testsuite/
+
+	* gcc.target/powerpc/dm-double-test.c: New test.
+	* lib/target-supports.exp (check_effective_target_ppc_dmr_ok): New
+	target test.
+
 ==================== Dmf003 branch, patch #13.
 
 Make MMA insns support dmr registers.
@@ -67,12 +73,6 @@ gcc/
 	(rs6000_split_multireg_move): Do not generate accumulator prime or
 	de-prime instructions if dense math.
 
-gcc/testsuite/
-
-	* gcc.target/powerpc/dm-double-test.c: New test.
-	* lib/target-supports.exp (check_effective_target_ppc_dmr_ok): New
-	target test.
-
 ==================== Dmf003 branch, patch #12.
 
 Add support for accumulators in DMR registers.

[gcc(refs/users/meissner/heads/dmf003)] Update ChangeLog.meissner.

[Michael Meissner]

https://gcc.gnu.org/g:a8146de8da3702c3d03d3c20cdf666dfb6601081

commit a8146de8da3702c3d03d3c20cdf666dfb6601081
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Nov 4 23:01:30 2022 -0400

    Update ChangeLog.meissner.
    
    2022-11-04   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * ChangeLog.meissner: Update.

Diff:
---
 gcc/ChangeLog.meissner | 18 ++++++------------
 1 file changed, 6 insertions(+), 12 deletions(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index d8f8c5ea6e6..bb8c5c1749e 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,15 +1,3 @@
-==================== Dmf003 branch, patch #15.
-
-Add dense math test.
-
-2022-11-04   Michael Meissner  <meissner@linux.ibm.com>
-
-gcc/testsuite/
-
-	* gcc.target/powerpc/dm-double-test.c: New test.
-	* lib/target-supports.exp (check_effective_target_ppc_dmr_ok): New
-	target test.
-
 ==================== Dmf003 branch, patch #14.
 
 Switch to dense math names for all MMA operations.
@@ -79,6 +67,12 @@ gcc/
 	(rs6000_split_multireg_move): Do not generate accumulator prime or
 	de-prime instructions if dense math.
 
+gcc/testsuite/
+
+	* gcc.target/powerpc/dm-double-test.c: New test.
+	* lib/target-supports.exp (check_effective_target_ppc_dmr_ok): New
+	target test.
+
 ==================== Dmf003 branch, patch #12.
 
 Add support for accumulators in DMR registers.

[gcc(refs/users/meissner/heads/dmf003)] Update ChangeLog.meissner.

[Michael Meissner]

https://gcc.gnu.org/g:8c32edea67b1eee4bb2ce419d0778c39a27b6376

commit 8c32edea67b1eee4bb2ce419d0778c39a27b6376
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Nov 4 19:24:34 2022 -0400

    Update ChangeLog.meissner.
    
    2022-11-04   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * ChangeLog.meissner: Update.

Diff:
---
 gcc/ChangeLog.meissner | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 38bd81cfe8c..d8f8c5ea6e6 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,15 @@
+==================== Dmf003 branch, patch #15.
+
+Add dense math test.
+
+2022-11-04   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/testsuite/
+
+	* gcc.target/powerpc/dm-double-test.c: New test.
+	* lib/target-supports.exp (check_effective_target_ppc_dmr_ok): New
+	target test.
+
 ==================== Dmf003 branch, patch #14.
 
 Switch to dense math names for all MMA operations.

[gcc(refs/users/meissner/heads/dmf003)] Update ChangeLog.meissner.

[Michael Meissner]

https://gcc.gnu.org/g:e1ca4eec7d615ea97ce54a5285c2c881ceb5e9e5

commit e1ca4eec7d615ea97ce54a5285c2c881ceb5e9e5
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Nov 4 18:55:43 2022 -0400

    Update ChangeLog.meissner.
    
    2022-11-04   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * ChangeLog.meissner: Update.

Diff:
---
 gcc/ChangeLog.meissner | 34 ++++++++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 74551e31877..38bd81cfe8c 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,37 @@
+==================== Dmf003 branch, patch #14.
+
+Switch to dense math names for all MMA operations.
+
+2022-11-04   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/mma.md (vvi4i4i8_dm): New int attribute.
+	(avvi4i4i8_dm): Likewise.
+	(vvi4i4i2_dm): Likewise.
+	(avvi4i4i2_dm): Likewise.
+	(vvi4i4_dm): Likewise.
+	(avvi4i4_dm): Likewise.
+	(pvi4i2_dm): Likewise.
+	(apvi4i2_dm): Likewise.
+	(vvi4i4i4_dm): Likewise.
+	(avvi4i4i4_dm): Likewise.
+	(mma_<vv>): Add support for running on DMF systems, generating the dense
+	math instruction and using the dense math accumulators.
+	(mma_<avv>): Likewise.
+	(mma_<pv>): Likewise.
+	(mma_<apv>): Likewise.
+	(mma_<vvi4i4i8>): Likewise.
+	(mma_<avvi4i4i8>): Likewise.
+	(mma_<vvi4i4i2>): Likewise.
+	(mma_<avvi4i4i2>): Likewise.
+	(mma_<vvi4i4>): Likewise.
+	(mma_<avvi4i4): Likewise.
+	(mma_<pvi4i2>): Likewise.
+	(mma_<apvi4i2): Likewise.
+	(mma_<vvi4i4i4>): Likewise.
+	(mma_<avvi4i4i4>): Likewise.
+
 ==================== Dmf003 branch, patch #13.
 
 Make MMA insns support dmr registers.

[gcc(refs/users/meissner/heads/dmf003)] Update ChangeLog.meissner.

[Michael Meissner]

https://gcc.gnu.org/g:f54f5ee5fdaa59cd144e160b314ea1d5664f4f6c

commit f54f5ee5fdaa59cd144e160b314ea1d5664f4f6c
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Nov 4 17:12:49 2022 -0400

    Update ChangeLog.meissner.
    
    2022-11-04   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * ChangeLog.meissner: Update.

Diff:
---
 gcc/ChangeLog.meissner | 142 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 142 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index dfa250ae86e..74551e31877 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,145 @@
+==================== Dmf003 branch, patch #13.
+
+Make MMA insns support dmr registers.
+
+2022-11-04   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/mma.md (mma_<acc>): New define_expand to handle
+	mma_<acc> for dense math and non dense math.
+	(mma_<acc> insn): Restrict to non dense math.
+	(mma_xxsetaccz): Convert to define_expand to handle non dense math and
+	dense math.
+	(mma_xxsetaccz_p10): Rename from mma_xxsetaccz and restrict usage to non
+	dense math.
+	(mma_xxsetaccz_dm): Dense math version of mma_xxsetaccz.
+	(mma_<vv>): Add support for dense math.
+	(mma_<avv>): Likewise.
+	(mma_<pv>): Likewise.
+	(mma_<apv>): Likewise.
+	(mma_<vvi4i4i8>): Likewise.
+	(mma_<avvi4i4i8>): Likewise.
+	(mma_<vvi4i4i2>): Likewise.
+	(mma_<avvi4i4i2>): Likewise.
+	(mma_<vvi4i4>): Likewise.
+	(mma_<avvi4i4>): Likewise.
+	(mma_<pvi4i2>): Likewise.
+	(mma_<apvi4i2>): Likewise.
+	(mma_<vvi4i4i4>): Likewise.
+	(mma_<avvi4i4i4>): Likewise.
+	* config/rs6000/rs6000.cc (print_operand): Make %A handle only DMRs if
+	dense math and only FPRs if not dense math.
+	(rs6000_split_multireg_move): Do not generate accumulator prime or
+	de-prime instructions if dense math.
+
+==================== Dmf003 branch, patch #12.
+
+Add support for accumulators in DMR registers.
+
+2022-11-04   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/constraints.md (wD constraint): New constraint.
+	* config/rs6000/mma.md (UNSPEC_DM_ASSEMBLE_ACC): New unspec.
+	(movxo): Convert into define_expand.
+	(movxo_fpr): Version of movxo where accumulators overlap with FPRs.
+	(movxo_dm): Dense math version of movxo.
+	(mma_assemble_acc): Add dense match support to define_expand.
+	(mma_assemble_acc_fpr): Rename from mma_assemble_acc, and restrict it to
+	non dense math.
+	(mma_assemble_acc_dm): Dense math version of mma_assemble_acc.
+	(mma_disassemble_acc): Add dense math support to define_expand.
+	(mma_disassemble_acc_fpr): Rename from mma_disassemble_acc, and restrict
+	it to non dense math.
+	(mma_disassemble_acc_dm): Dense math version of mma_disassemble_acc.
+	* config/rs6000/predicates.md (dmr_operand): New predicate.
+	(accumulator_operand): Likewise.
+	* config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS): Add -mdense-math.
+	(POWERPC_MASKS): Likewise.
+	* config/rs6000/rs6000.cc (enum rs6000_reg_type): Add DMR_REG_TYPE.
+	(enum rs6000_reload_reg_type): Add RELOAD_REG_DMR.
+	(LAST_RELOAD_REG_CLASS): Add support for DMR registers.
+	(reload_reg_map): Likewise.
+	(rs6000_reg_names): Likewise.
+	(alt_reg_names): Likewise.
+	(rs6000_hard_regno_nregs_internal): Likewise.
+	(rs6000_hard_regno_mode_ok_uncached): Likewise.
+	(rs6000_debug_reg_global): Likewise.
+	(rs6000_setup_reg_addr_masks): Likewise.
+	(rs6000_init_hard_regno_mode_ok): Likewise.
+	(rs6000_option_override_internal): Add checking for -mdense-math.
+	(rs6000_secondary_reload_memory): Add support for DMR registers.
+	(rs6000_secondary_reload_simple_move): Likewise.
+	(rs6000_preferred_reload_class): Likewise.
+	(rs6000_secondary_reload_class): Likewise.
+	(print_operand): Make %A handle both FPRs and DMRs.
+	(rs6000_dmr_register_move_cost): New helper function.
+	(rs6000_register_move_cost): Add support for DMR registers.
+	(rs6000_memory_move_cost): Likewise.
+	(rs6000_compute_pressure_classes): Likewise.
+	(rs6000_debugger_regno): Likewise.
+	(rs6000_opt_masks): Add -mdense-math.
+	(rs6000_split_multireg_move): Add support for DMRs.
+	* config/rs6000/rs6000.h (UNITS_PER_DMR_WORD): New macro.
+	(FIRST_PSEUDO_REGISTER): Update for DMRs.
+	(FIXED_REGISTERS): Add DMRs.
+	(CALL_REALLY_USED_REGISTERS): Likewise.
+	(REG_ALLOC_ORDER): Likewise.
+	(enum reg_class): Add DM_REGS.
+	(REG_CLASS_NAMES): Likewise.
+	(REG_CLASS_CONTENTS): Likewise.
+	* config/rs6000/rs6000.md (FIRST_DMR_REGNO): New constant.
+	(LAST_DMR_REGNO): Likewise.
+	(isa attribute): Add 'dm' and 'not_dm' attributes.
+	(enabled attribute): Support 'dm' and 'not_dm' attributes.
+	* config/rs6000/rs6000.opt (-mdense-math): New switch.
+	* doc/md.texi (PowerPC constraints): Document wD constraint.
+
+==================== Dmf003 branch, patch #11.
+
+Make -mcpu=future enable -mblock-ops-vector-pair.
+
+2022-11-04   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS): Add
+	-mblock-ops-vector-pair.
+	(POWERPC_MASKS): Likewise.
+
+==================== Dmf003 branch, patch #10.
+
+Add -mcpu=future.
+
+2022-11-04   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define
+	__ARCH_PWR_FUTURE__ if -mcpu=future.
+	* config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS): New macro.
+	(POWERPC_MASKS): Add -mfuture.
+	* config/rs6000/rs6000-opts.h (enum processor_type): Add
+	PROCESSOR_FUTURE.
+	* config/rs6000/rs6000-tables.opt: Regenerate.
+	* config/rs6000/rs6000.cc (rs6000_option_override_internal): Add
+	-mcpu=future support.  Make -mtune=future act like -mtune=power10 for
+	now.
+	(rs6000_machine_from_flags): Likewise.
+	(rs6000_reassociation_width): Likewise.
+	(rs6000_adjust_cost): Likewise.
+	(rs6000_issue_rate): Likewise.
+	(rs6000_sched_reorder): Likewise.
+	(rs6000_sched_reorder2): Likewise.
+	(rs6000_register_move_cost): Likewise.
+	(rs6000_opt_masks): Add -mfuture.
+	* config/rs6000/rs6000.h (ASM_CPU_SUPPORT): Likewise.
+	* config/rs6000/rs6000.opt (-mfuture): New undocumented debug switch.
+	* config/rs6000/rs6000.md (cpu attribute): Add -mcpu=future support.
+	* doc/invoke.texi (IBM RS/6000 and PowerPC Options): Document -mcpu=future.
+
 ==================== Dmf003 branch, patch #6 was reverted.
 
 ==================== Dmf003 branch, patch #5 was reverted.

[gcc(refs/users/meissner/heads/dmf003)] Update ChangeLog.meissner.

[Michael Meissner]

https://gcc.gnu.org/g:57aeecc1243ce4d048f88c1093020d50d28eff8a

commit 57aeecc1243ce4d048f88c1093020d50d28eff8a
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Nov 4 13:08:52 2022 -0400

    Update ChangeLog.meissner.
    
    2022-11-04   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * ChangeLog.meissner: Update.

Diff:
---
 gcc/ChangeLog.meissner | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 47eef9fce7b..30a15aee021 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,18 @@
+==================== Dmf003 branch, patch #6.
+
+Fix typos.
+
+2022-11-04   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/mma.md (movxo_dm): Fix typos.
+	(mma_assemble_acc_dm): Likewise.
+	(mma_disassemble_acc_dm): Likewise.
+	(movtdo_insert512_upper): Likewise.
+	(movtdo_insert512_lower): Likewise.
+	(movtdo_extract512): Likewise.
+
 ==================== Dmf003 branch, patch #5.
 
 Add LAGEN and PLAGEN support.

[gcc(refs/users/meissner/heads/dmf003)] Update ChangeLog.meissner.

[Michael Meissner]

https://gcc.gnu.org/g:f911f7828fa6d48e4b1e3ef424697f787426c554

commit f911f7828fa6d48e4b1e3ef424697f787426c554
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Nov 4 03:14:12 2022 -0400

    Update ChangeLog.meissner.
    
    2022-11-04   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * ChangeLog.meissner: Update.

Diff:
---
 gcc/ChangeLog.meissner | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index b4b47b0ac06..313ab34ee01 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -22,7 +22,7 @@ gcc/
 	support.
 	(rs6000_init_builtins): Add support for __dmr keyword.
 	* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define
-	__DENSE_MATH__ if we have dense math support.
+	__PPC_DMR__ if we have dense math support.
 	* config/rs6000/rs6000-call.cc (rs6000_return_in_memory): Add support
 	for TDOmode.
 	(rs6000_function_arg): Likewise.

[gcc(refs/users/meissner/heads/dmf003)] Update ChangeLog.meissner.

[Michael Meissner]

https://gcc.gnu.org/g:4d65f8b02603b9075f01fa1bc5c886d9a40229fd

commit 4d65f8b02603b9075f01fa1bc5c886d9a40229fd
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Nov 4 02:38:27 2022 -0400

    Update ChangeLog.meissner.
    
    2022-11-04   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * ChangeLog.meissner: Update.

Diff:
---
 gcc/ChangeLog.meissner | 196 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 196 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 04a6f7c32ea..b4b47b0ac06 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,199 @@
+==================== Dmf003 branch, patch #1.
+
+Add support for 1,024 bit DMR registers.
+
+2022-10-26   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/mma.md (UNSPEC_DM_INSERT512_UPPER): New unspec.
+	(UNSPEC_DM_INSERT512_LOWER): Likewise.
+	(UNSPEC_DM_EXTRACT512): Likewise.
+	(UNSPEC_DMR_RELOAD_FROM_MEMORY): Likewise.
+	(UNSPEC_DMR_RELOAD_TO_MEMORY): Likewise.
+	(movtdo): New define_expand and define_insn_and_split to implement 1,024
+	bit DMR registers.
+	(movtdo_insert512_upper): New insn.
+	(movtdo_insert512_lower): Likewise.
+	(movtdo_extract512): Likewise.
+	(reload_dmr_from_memory): Likewise.
+	(reload_dmr_to_memory): Likewise.
+	* config/rs6000/rs6000-builtin.cc (rs6000_type_string): Add DMR
+	support.
+	(rs6000_init_builtins): Add support for __dmr keyword.
+	* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define
+	__DENSE_MATH__ if we have dense math support.
+	* config/rs6000/rs6000-call.cc (rs6000_return_in_memory): Add support
+	for TDOmode.
+	(rs6000_function_arg): Likewise.
+	* config/rs6000/rs6000-modes.def (TDOmode): New mode.
+	* config/rs6000/rs6000.cc (rs6000_hard_regno_nregs_internal): Add
+	support for TDOmode.
+	(rs6000_hard_regno_mode_ok_uncached): Likewise.
+	(rs6000_hard_regno_mode_ok): Likewise.
+	(rs6000_modes_tieable_p): Likewise.
+	(rs6000_debug_reg_global): Likewise.
+	(rs6000_setup_reg_addr_masks): Likewise.
+	(rs6000_init_hard_regno_mode_ok): Add support for TDOmode.  Setup reload
+	hooks for DMR mode.
+	(reg_offset_addressing_ok_p): Add support for TDOmode.
+	(rs6000_emit_move): Likewise.
+	(rs6000_secondary_reload_simple_move): Likewise.
+	(rs6000_secondary_reload_class): Likewise.
+	(rs6000_mangle_type): Add mangling for __dmr type.
+	(rs6000_dmr_register_move_cost): Add support for TDOmode.
+	(rs6000_split_multireg_move): Likewise.
+	(rs6000_invalid_conversion): Likewise.
+	* config/rs6000/rs6000.h (VECTOR_ALIGNMENT_P): Add TDOmode.
+	(enum rs6000_builtin_type_index): Add DMR type nodes.
+	(dmr_type_node): Likewise.
+	(ptr_dmr_type_node): Likewise.
+
+==================== Dmf003 branch, patch #1.
+
+Switch to dense math names for all MMA operations.
+
+2022-10-26   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/mma.md (vvi4i4i8_dm): New int attribute.
+	(avvi4i4i8_dm): Likewise.
+	(vvi4i4i2_dm): Likewise.
+	(avvi4i4i2_dm): Likewise.
+	(vvi4i4_dm): Likewise.
+	(avvi4i4_dm): Likewise.
+	(pvi4i2_dm): Likewise.
+	(apvi4i2_dm): Likewise.
+	(vvi4i4i4_dm): Likewise.
+	(avvi4i4i4_dm): Likewise.
+	(mma_<vv>): Add support for running on DMF systems, generating the dense
+	math instruction and using the dense math accumulator.
+	(mma_<avv>): Likewise.
+	(mma_<pv>): Likewise.
+	(mma_<apv>): Likewise.
+	(mma_<vvi4i4i8>): Likewise.
+	(mma_<avvi4i4i8>): Likewise.
+	(mma_<vvi4i4i2>): Likewise.
+	(mma_<avvi4i4i2>): Likewise.
+	(mma_<vvi4i4>): Likewise.
+	(mma_<avvi4i4): Likewise.
+	(mma_<pvi4i2>): Likewise.
+	(mma_<apvi4i2): Likewise.
+	(mma_<vvi4i4i4>): Likewise.
+	(mma_<avvi4i4i4>): Likewise.
+
+==================== Dmf003 branch, patch #1.
+
+Add support for accumulators in DMR registers.
+
+2022-10-26   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/constraints.md (wD constraint): New constraint.
+	* config/rs6000/mma.md (UNSPEC_DM_ASSEMBLE_ACC): New unspec.
+	(movxo): Convert into define_expand.
+	(movxo_p10): Power10 version of movxo.
+	(movxo_dm): Dense math version of movxo.
+	(mma_assemble_acc): Add dense match support to define_expand.
+	(mma_assemble_acc_p10): Rename from mma_assemble_acc, and restrict it to
+	non dense math.
+	(mma_assemble_acc_dm): Dense math version of mma_assemble_acc.
+	(mma_disassemble_acc): Add dense math support to define_expand.
+	(mma_disassemble_acc_p10): Rename from mma_disassemble_acc, and restrict
+	it to non dense math.
+	(mma_disassemble_acc_dm): Dense math version of mma_disassemble_acc.
+	(mma_<acc>): New define_expand to handle mma_<acc> for dense math and
+	non dense math.
+	(mma_<acc> insn): Restrict to non dense math.
+	(mma_xxsetaccz): Convert to define_expand to handle non dense math and
+	dense math.
+	(mma_xxsetaccz_p10): Rename from mma_xxsetaccz and restrict usage to non
+	dense math.
+	(mma_xxsetaccz_dm): Dense math version of mma_xxsetaccz.
+	(mma_<vv>): Add support for dense math.
+	(mma_<avv>): Likewise.
+	(mma_<pv>): Likewise.
+	(mma_<apv>): Likewise.
+	(mma_<vvi4i4i8>): Likewise.
+	(mma_<avvi4i4i8>): Likewise.
+	(mma_<vvi4i4i2>): Likewise.
+	(mma_<avvi4i4i2>): Likewise.
+	(mma_<vvi4i4>): Likewise.
+	(mma_<avvi4i4>): Likewise.
+	(mma_<pvi4i2>): Likewise.
+	(mma_<apvi4i2>): Likewise.
+	(mma_<vvi4i4i4>): Likewise.
+	(mma_<avvi4i4i4>): Likewise.
+	* config/rs6000/predicates.md (dmr_operand): New predicate.
+	(accumulator_operand): Likewise.
+	* config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS): Add -mdense-math.
+	(POWERPC_MASKS): Likewise.
+	* config/rs6000/rs6000.cc (enum rs6000_reg_type): Add DMR_REG_TYPE.
+	(enum rs6000_reload_reg_type): Add RELOAD_REG_DMR.
+	(LAST_RELOAD_REG_CLASS): Add support for DMR registers.
+	(reload_reg_map): Likewise.
+	(rs6000_reg_names): Likewise.
+	(alt_reg_names): Likewise.
+	(rs6000_hard_regno_nregs_internal): Likewise.
+	(rs6000_hard_regno_mode_ok_uncached): Likewise.
+	(rs6000_debug_reg_global): Likewise.
+	(rs6000_setup_reg_addr_masks): Likewise.
+	(rs6000_init_hard_regno_mode_ok): Likewise.
+	(rs6000_option_override_internal): Add checking for -mdense-math.
+	(rs6000_secondary_reload_memory): Add support for DMR registers.
+	(rs6000_secondary_reload_simple_move): Likewise.
+	(rs6000_preferred_reload_class): Likewise.
+	(rs6000_secondary_reload_class): Likewise.
+	(print_operand): Make %A handle both FPRs and DMRs.
+	(rs6000_dmr_register_move_cost): New helper function.
+	(rs6000_register_move_cost): Add support for DMR registers.
+	(rs6000_memory_move_cost): Likewise.
+	(rs6000_compute_pressure_classes): Likewise.
+	(rs6000_debugger_regno): Likewise.
+	(rs6000_opt_masks): Add -mdense-math.
+	(rs6000_split_multireg_move): Add support for DMRs.
+	* config/rs6000/rs6000.h (UNITS_PER_DMR_WORD): New macro.
+	(FIRST_PSEUDO_REGISTER): Update for DMRs.
+	(FIXED_REGISTERS): Add DMRs.
+	(CALL_REALLY_USED_REGISTERS): Likewise.
+	(REG_ALLOC_ORDER): Likewise.
+	(enum reg_class): Add DM_REGS.
+	(REG_CLASS_NAMES): Likewise.
+	(REG_CLASS_CONTENTS): Likewise.
+	* config/rs6000/rs6000.md (FIRST_DMR_REGNO): New constant.
+	(LAST_DMR_REGNO): Likewise.
+	(isa attribute): Add 'dm' and 'not_dm' attributes.
+	(enabled attribute): Support 'dm' and 'not_dm' attributes.
+	* config/rs6000/rs6000.opt (-mdense-math): New switch.
+
+==================== Dmf003 branch, patch #1.
+
+Add -mcpu=future.
+
+2022-10-26   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS): New macro.
+	(POWERPC_MASKS): Add -mblock-ops-vector-pair.
+	* config/rs6000/rs6000-opts.h (enum processor_type): Add
+	PROCESSOR_FUTURE.
+	* config/rs6000/rs6000-tables.opt: Regenerate.
+	* config/rs6000/rs6000.cc (rs6000_option_override_internal): Add
+	-mcpu=future support.
+	(rs6000_machine_from_flags): Likewise.
+	(rs6000_adjust_cost): Likewise.
+	(rs6000_issue_rate): Likewise.
+	(rs6000_sched_reorder): Likewise.
+	(rs6000_sched_reorder2): Likewise.
+	(rs6000_register_move_cost): Likewise.
+	* config/rs6000/rs6000.h (ASM_CPU_SUPPORT): Likewise.
+	* config/rs6000/rs6000.md (cpu attribute): Likewise.
+
+==================== Dmf003 branch, clone branch.
+
 2022-11-04   Michael Meissner  <meissner@linux.ibm.com>
 
 	Clone branch