[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: branch-(not)equals-zero compares against $zero

[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: branch-(not)equals-zero compares against $zero

[Philipp Tomsich]

https://gcc.gnu.org/g:a3f8b493b4a4e82c80ba1e5ec5c4bd1553e41894

commit a3f8b493b4a4e82c80ba1e5ec5c4bd1553e41894
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date:   Sun Aug 30 21:02:36 2020 +0200

    RISC-V: branch-(not)equals-zero compares against $zero
    
    If we are testing a register or a paradoxical subreg (i.e. anything that is not
    a partial subreg) for equality/non-equality with zero, we can generate a branch
    that compares against $zero.  This will work for QI, HI, SI and DImode, so we
    enable this for ANYI.
    
    2020-08-30  gcc/ChangeLog:
    
            * config/riscv/riscv.md (*branch<mode>_equals_zero): Added pattern.
    
    Series-to: gcc-patches@gcc.gnu.org
    Series-cc: Palmer Dabbelt <palmer@rivosinc.com>
    Series-cc: Vineet Gupta <vineetg@rivosinc.com>
    Series-cc: Christoph Muellner <christoph.muellner@vrull.eu>
    Series-cc: Kito Cheng <kito.cheng@gmail.com>
    Series-cc: Jeff Law <jlaw@ventanamicro.com>

Diff:
---
 gcc/config/riscv/riscv.md | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 532289dd178..1107b61e905 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -2208,6 +2208,19 @@
 
 ;; Conditional branches
 
+(define_insn "*branch<mode>_equals_zero"
+  [(set (pc)
+	(if_then_else
+	 (match_operator 1 "equality_operator"
+			 [(match_operand:ANYI 2 "register_operand" "r")
+			  (const_int 0)])
+	 (label_ref (match_operand 0 "" ""))
+	 (pc)))]
+  "!partial_subreg_p (operands[2])"
+  "b%C1\t%2,zero,%0"
+  [(set_attr "type" "branch")
+   (set_attr "mode" "none")])
+
 (define_insn "*branch<mode>"
   [(set (pc)
 	(if_then_else

[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: branch-(not)equals-zero compares against $zero

[Philipp Tomsich]

https://gcc.gnu.org/g:3bace604d0bee73ecd030133de2db09124014ce8

commit 3bace604d0bee73ecd030133de2db09124014ce8
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date:   Sun Aug 30 21:02:36 2020 +0200

    RISC-V: branch-(not)equals-zero compares against $zero
    
    If we are testing a register or a paradoxical subreg (i.e. anything that is not
    a partial subreg) for equality/non-equality with zero, we can generate a branch
    that compares against $zero.  This will work for QI, HI, SI and DImode, so we
    enable this for ANYI.
    
    2020-08-30  gcc/ChangeLog:
    
            * config/riscv/riscv.md (*branch<mode>_equals_zero): Added pattern.
    
    Series-to: gcc-patches@gcc.gnu.org
    Series-cc: Palmer Dabbelt <palmer@rivosinc.com>
    Series-cc: Vineet Gupta <vineetg@rivosinc.com>
    Series-cc: Christoph Muellner <christoph.muellner@vrull.eu>
    Series-cc: Kito Cheng <kito.cheng@gmail.com>
    Series-cc: Jeff Law <jlaw@ventanamicro.com>

Diff:
---
 gcc/config/riscv/riscv.md | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index b7bb338ac04..b616c1915df 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -2267,6 +2267,19 @@
 	operands[7] = GEN_INT (leading + trailing);
 })
 
+(define_insn "*branch<mode>_equals_zero"
+  [(set (pc)
+	(if_then_else
+	 (match_operator 1 "equality_operator"
+			 [(match_operand:ANYI 2 "register_operand" "r")
+			  (const_int 0)])
+	 (label_ref (match_operand 0 "" ""))
+	 (pc)))]
+  "!partial_subreg_p (operands[2])"
+  "b%C1\t%2,zero,%0"
+  [(set_attr "type" "branch")
+   (set_attr "mode" "none")])
+
 (define_insn "*branch<mode>"
   [(set (pc)
 	(if_then_else

[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: branch-(not)equals-zero compares against $zero

[Philipp Tomsich]

https://gcc.gnu.org/g:800ff3743bc2d47f30331dc802da5ae8e70db8ca

commit 800ff3743bc2d47f30331dc802da5ae8e70db8ca
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date:   Sun Aug 30 21:02:36 2020 +0200

    RISC-V: branch-(not)equals-zero compares against $zero
    
    If we are testing a register or a paradoxical subreg (i.e. anything that is not
    a partial subreg) for equality/non-equality with zero, we can generate a branch
    that compares against $zero.  This will work for QI, HI, SI and DImode, so we
    enable this for ANYI.
    
    2020-08-30  gcc/ChangeLog:
    
            * config/riscv/riscv.md (*branch<mode>_equals_zero): Added pattern.
    
    Series-to: gcc-patches@gcc.gnu.org
    Series-cc: Palmer Dabbelt <palmer@rivosinc.com>
    Series-cc: Vineet Gupta <vineetg@rivosinc.com>
    Series-cc: Christoph Muellner <christoph.muellner@vrull.eu>
    Series-cc: Kito Cheng <kito.cheng@gmail.com>
    Series-cc: Jeff Law <jlaw@ventanamicro.com>

Diff:
---
 gcc/config/riscv/riscv.md | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index b7bb338ac04..b616c1915df 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -2267,6 +2267,19 @@
 	operands[7] = GEN_INT (leading + trailing);
 })
 
+(define_insn "*branch<mode>_equals_zero"
+  [(set (pc)
+	(if_then_else
+	 (match_operator 1 "equality_operator"
+			 [(match_operand:ANYI 2 "register_operand" "r")
+			  (const_int 0)])
+	 (label_ref (match_operand 0 "" ""))
+	 (pc)))]
+  "!partial_subreg_p (operands[2])"
+  "b%C1\t%2,zero,%0"
+  [(set_attr "type" "branch")
+   (set_attr "mode" "none")])
+
 (define_insn "*branch<mode>"
   [(set (pc)
 	(if_then_else

[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: branch-(not)equals-zero compares against $zero

[Philipp Tomsich]

https://gcc.gnu.org/g:d0a7eb78c188948b59a16d4f658851ab2a4d4e13

commit d0a7eb78c188948b59a16d4f658851ab2a4d4e13
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date:   Sun Aug 30 21:02:36 2020 +0200

    RISC-V: branch-(not)equals-zero compares against $zero
    
    If we are testing a register or a paradoxical subreg (i.e. anything that is not
    a partial subreg) for equality/non-equality with zero, we can generate a branch
    that compares against $zero.  This will work for QI, HI, SI and DImode, so we
    enable this for ANYI.
    
    2020-08-30  gcc/ChangeLog:
    
            * config/riscv/riscv.md (*branch<mode>_equals_zero): Added pattern.
    
    Series-to: gcc-patches@gcc.gnu.org
    Series-cc: Palmer Dabbelt <palmer@rivosinc.com>
    Series-cc: Vineet Gupta <vineetg@rivosinc.com>
    Series-cc: Christoph Muellner <christoph.muellner@vrull.eu>
    Series-cc: Kito Cheng <kito.cheng@gmail.com>
    Series-cc: Jeff Law <jlaw@ventanamicro.com>

Diff:
---
 gcc/config/riscv/riscv.md | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 0469882c80d..3d4a1cba096 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -2216,6 +2216,19 @@
 
 ;; Conditional branches
 
+(define_insn "*branch<mode>_equals_zero"
+  [(set (pc)
+	(if_then_else
+	 (match_operator 1 "equality_operator"
+			 [(match_operand:ANYI 2 "register_operand" "r")
+			  (const_int 0)])
+	 (label_ref (match_operand 0 "" ""))
+	 (pc)))]
+  "!partial_subreg_p (operands[2])"
+  "b%C1\t%2,zero,%0"
+  [(set_attr "type" "branch")
+   (set_attr "mode" "none")])
+
 (define_insn "*branch<mode>"
   [(set (pc)
 	(if_then_else

[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: branch-(not)equals-zero compares against $zero

[Philipp Tomsich]

https://gcc.gnu.org/g:920c4e200b48631e7ddb8f213f031fb3ecb333ef

commit 920c4e200b48631e7ddb8f213f031fb3ecb333ef
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date:   Sun Aug 30 21:02:36 2020 +0200

    RISC-V: branch-(not)equals-zero compares against $zero
    
    If we are testing a register or a paradoxical subreg (i.e. anything that is not
    a partial subreg) for equality/non-equality with zero, we can generate a branch
    that compares against $zero.  This will work for QI, HI, SI and DImode, so we
    enable this for ANYI.
    
    2020-08-30  gcc/ChangeLog:
    
            * config/riscv/riscv.md (*branch<mode>_equals_zero): Added pattern.
    
    Series-to: gcc-patches@gcc.gnu.org
    Series-cc: Palmer Dabbelt <palmer@rivosinc.com>
    Series-cc: Vineet Gupta <vineetg@rivosinc.com>
    Series-cc: Christoph Muellner <christoph.muellner@vrull.eu>
    Series-cc: Kito Cheng <kito.cheng@gmail.com>
    Series-cc: Jeff Law <jlaw@ventanamicro.com>

Diff:
---
 gcc/config/riscv/riscv.md | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 0469882c80d..3d4a1cba096 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -2216,6 +2216,19 @@
 
 ;; Conditional branches
 
+(define_insn "*branch<mode>_equals_zero"
+  [(set (pc)
+	(if_then_else
+	 (match_operator 1 "equality_operator"
+			 [(match_operand:ANYI 2 "register_operand" "r")
+			  (const_int 0)])
+	 (label_ref (match_operand 0 "" ""))
+	 (pc)))]
+  "!partial_subreg_p (operands[2])"
+  "b%C1\t%2,zero,%0"
+  [(set_attr "type" "branch")
+   (set_attr "mode" "none")])
+
 (define_insn "*branch<mode>"
   [(set (pc)
 	(if_then_else