[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Implement movmisalign<mode> to enable SLP

[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Implement movmisalign<mode> to enable SLP

[Philipp Tomsich]

https://gcc.gnu.org/g:3c9bac450f7f5cb5df7bdd6a118f95b1ff3a2cc2

commit 3c9bac450f7f5cb5df7bdd6a118f95b1ff3a2cc2
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date:   Wed Nov 9 12:54:32 2022 +0100

    RISC-V: Implement movmisalign<mode> to enable SLP
    
    The default implementation of support_vector_misalignment() checks
    whether movmisalign<mode> is present for the requested mode.  This
    will be used by vect_supportable_dr_alignment() to determine whether a
    misaligned access of vectorized data is permissible.
    
    For RISC-V this is required to convert multiple integer data refs,
    such as "c[1] << 8) | c[0]" into a larger (in the example before: a
    halfword load) access.
    We conditionalize on !riscv_slow_unaligned_access_p to allow the
    misaligned refs, if they are not expected to be slow.
    
    This benefits both xalancbmk and blender on SPEC CPU 2017.
    
    gcc/ChangeLog:
    
            * config/riscv/riscv.md (movmisalign<mode>): Implement.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/movmisalign-1.c: New test.
            * gcc.target/riscv/movmisalign-2.c: New test.
            * gcc.target/riscv/movmisalign-3.c: New test.
    
    Series-to: gcc-patches@gcc.gnu.org
    Series-cc: Palmer Dabbelt <palmer@rivosinc.com>
    Series-cc: Vineet Gupta <vineetg@rivosinc.com>
    Series-cc: Christoph Muellner <christoph.muellner@vrull.eu>
    Series-cc: Kito Cheng <kito.cheng@gmail.com>
    Series-cc: Jeff Law <jlaw@ventanamicro.com>

Diff:
---
 gcc/config/riscv/riscv.md                      | 18 ++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movmisalign-1.c | 12 ++++++++++++
 gcc/testsuite/gcc.target/riscv/movmisalign-2.c | 12 ++++++++++++
 gcc/testsuite/gcc.target/riscv/movmisalign-3.c | 12 ++++++++++++
 4 files changed, 54 insertions(+)

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 64bf30f7720..3e61a8b90ab 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -1718,6 +1718,24 @@
 		      MAX_MACHINE_MODE, &operands[3], TRUE);
 })
 
+;; Misaligned (integer) moves: provide an implementation for
+;; movmisalign, so the default support_vector_misalignment() will
+;; return the right boolean depending on whether
+;; riscv_slow_unaligned_access_p is set or not.
+;;
+;; E.g., this is needed for SLP to convert "c[1] << 8) | c[0]" into a
+;; HImode load (a good test case will be blender and xalancbmk in SPEC
+;; CPU 2017).
+;;
+(define_expand "movmisalign<mode>"
+  [(set (match_operand:ANYI 0 "")
+	(match_operand:ANYI 1 ""))]
+  "!riscv_slow_unaligned_access_p"
+{
+  if (riscv_legitimize_move (<MODE>mode, operands[0], operands[1]))
+    DONE;
+})
+
 ;; 64-bit integer moves
 
 (define_expand "movdi"
diff --git a/gcc/testsuite/gcc.target/riscv/movmisalign-1.c b/gcc/testsuite/gcc.target/riscv/movmisalign-1.c
new file mode 100644
index 00000000000..791a3d63335
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movmisalign-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64 -mtune=size" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" } } */
+
+void f(unsigned short *sink, unsigned char *arr)
+{
+  *sink = (arr[1] << 8) | arr[0];
+}
+
+/* { dg-final { scan-assembler-times "lhu\t" 1 } } */
+/* { dg-final { scan-assembler-not "lbu\t" } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/movmisalign-2.c b/gcc/testsuite/gcc.target/riscv/movmisalign-2.c
new file mode 100644
index 00000000000..ef73dcb2d9d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movmisalign-2.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64 -mtune=size -mstrict-align" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" } } */
+
+void f(unsigned short *sink, unsigned char *arr)
+{
+  *sink = (arr[1] << 8) | arr[0];
+}
+
+/* { dg-final { scan-assembler-times "lbu\t" 2 } } */
+/* { dg-final { scan-assembler-not "lhu\t" } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/movmisalign-3.c b/gcc/testsuite/gcc.target/riscv/movmisalign-3.c
new file mode 100644
index 00000000000..963b11c27fd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movmisalign-3.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64 -mtune=rocket" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" } } */
+
+void f(unsigned short *sink, unsigned char *arr)
+{
+  *sink = (arr[1] << 8) | arr[0];
+}
+
+/* { dg-final { scan-assembler-times "lbu\t" 2 } } */
+/* { dg-final { scan-assembler-not "lhu\t" } } */
+

[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Implement movmisalign<mode> to enable SLP

[Philipp Tomsich]

https://gcc.gnu.org/g:4139aa365b3d26a9348de4bb397b09c2687aa8c6

commit 4139aa365b3d26a9348de4bb397b09c2687aa8c6
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date:   Wed Nov 9 12:54:32 2022 +0100

    RISC-V: Implement movmisalign<mode> to enable SLP
    
    The default implementation of support_vector_misalignment() checks
    whether movmisalign<mode> is present for the requested mode.  This
    will be used by vect_supportable_dr_alignment() to determine whether a
    misaligned access of vectorized data is permissible.
    
    For RISC-V this is required to convert multiple integer data refs,
    such as "c[1] << 8) | c[0]" into a larger (in the example before: a
    halfword load) access.
    We conditionalize on !riscv_slow_unaligned_access_p to allow the
    misaligned refs, if they are not expected to be slow.
    
    This benefits both xalancbmk and blender on SPEC CPU 2017.
    
    gcc/ChangeLog:
    
            * config/riscv/riscv.md (movmisalign<mode>): Implement.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/movmisalign-1.c: New test.
            * gcc.target/riscv/movmisalign-2.c: New test.
            * gcc.target/riscv/movmisalign-3.c: New test.
    
    Series-to: gcc-patches@gcc.gnu.org
    Series-cc: Palmer Dabbelt <palmer@rivosinc.com>
    Series-cc: Vineet Gupta <vineetg@rivosinc.com>
    Series-cc: Christoph Muellner <christoph.muellner@vrull.eu>
    Series-cc: Kito Cheng <kito.cheng@gmail.com>
    Series-cc: Jeff Law <jlaw@ventanamicro.com>

Diff:
---
 gcc/config/riscv/riscv.md                      | 18 ++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movmisalign-1.c | 12 ++++++++++++
 gcc/testsuite/gcc.target/riscv/movmisalign-2.c | 12 ++++++++++++
 gcc/testsuite/gcc.target/riscv/movmisalign-3.c | 12 ++++++++++++
 4 files changed, 54 insertions(+)

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 20cdb7ecfe0..5e659148403 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -1721,6 +1721,24 @@
 		      MAX_MACHINE_MODE, &operands[3], TRUE);
 })
 
+;; Misaligned (integer) moves: provide an implementation for
+;; movmisalign, so the default support_vector_misalignment() will
+;; return the right boolean depending on whether
+;; riscv_slow_unaligned_access_p is set or not.
+;;
+;; E.g., this is needed for SLP to convert "c[1] << 8) | c[0]" into a
+;; HImode load (a good test case will be blender and xalancbmk in SPEC
+;; CPU 2017).
+;;
+(define_expand "movmisalign<mode>"
+  [(set (match_operand:ANYI 0 "")
+	(match_operand:ANYI 1 ""))]
+  "!riscv_slow_unaligned_access_p"
+{
+  if (riscv_legitimize_move (<MODE>mode, operands[0], operands[1]))
+    DONE;
+})
+
 ;; 64-bit integer moves
 
 (define_expand "movdi"
diff --git a/gcc/testsuite/gcc.target/riscv/movmisalign-1.c b/gcc/testsuite/gcc.target/riscv/movmisalign-1.c
new file mode 100644
index 00000000000..791a3d63335
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movmisalign-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64 -mtune=size" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" } } */
+
+void f(unsigned short *sink, unsigned char *arr)
+{
+  *sink = (arr[1] << 8) | arr[0];
+}
+
+/* { dg-final { scan-assembler-times "lhu\t" 1 } } */
+/* { dg-final { scan-assembler-not "lbu\t" } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/movmisalign-2.c b/gcc/testsuite/gcc.target/riscv/movmisalign-2.c
new file mode 100644
index 00000000000..ef73dcb2d9d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movmisalign-2.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64 -mtune=size -mstrict-align" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" } } */
+
+void f(unsigned short *sink, unsigned char *arr)
+{
+  *sink = (arr[1] << 8) | arr[0];
+}
+
+/* { dg-final { scan-assembler-times "lbu\t" 2 } } */
+/* { dg-final { scan-assembler-not "lhu\t" } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/movmisalign-3.c b/gcc/testsuite/gcc.target/riscv/movmisalign-3.c
new file mode 100644
index 00000000000..963b11c27fd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movmisalign-3.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64 -mtune=rocket" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" } } */
+
+void f(unsigned short *sink, unsigned char *arr)
+{
+  *sink = (arr[1] << 8) | arr[0];
+}
+
+/* { dg-final { scan-assembler-times "lbu\t" 2 } } */
+/* { dg-final { scan-assembler-not "lhu\t" } } */
+

[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Implement movmisalign<mode> to enable SLP

[Philipp Tomsich]

https://gcc.gnu.org/g:015bb8087bce8ec024a8b12648d6fd7b98650dcc

commit 015bb8087bce8ec024a8b12648d6fd7b98650dcc
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date:   Wed Nov 9 12:54:32 2022 +0100

    RISC-V: Implement movmisalign<mode> to enable SLP
    
    The default implementation of support_vector_misalignment() checks
    whether movmisalign<mode> is present for the requested mode.  This
    will be used by vect_supportable_dr_alignment() to determine whether a
    misaligned access of vectorized data is permissible.
    
    For RISC-V this is required to convert multiple integer data refs,
    such as "c[1] << 8) | c[0]" into a larger (in the example before: a
    halfword load) access.
    We conditionalize on !riscv_slow_unaligned_access_p to allow the
    misaligned refs, if they are not expected to be slow.
    
    This benefits both xalancbmk and blender on SPEC CPU 2017.
    
    gcc/ChangeLog:
    
            * config/riscv/riscv.md (movmisalign<mode>): Implement.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/movmisalign-1.c: New test.
            * gcc.target/riscv/movmisalign-2.c: New test.
            * gcc.target/riscv/movmisalign-3.c: New test.
    
    Series-to: gcc-patches@gcc.gnu.org
    Series-cc: Palmer Dabbelt <palmer@rivosinc.com>
    Series-cc: Vineet Gupta <vineetg@rivosinc.com>
    Series-cc: Christoph Muellner <christoph.muellner@vrull.eu>
    Series-cc: Kito Cheng <kito.cheng@gmail.com>
    Series-cc: Jeff Law <jlaw@ventanamicro.com>

Diff:
---
 gcc/config/riscv/riscv.md                      | 18 ++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movmisalign-1.c | 12 ++++++++++++
 gcc/testsuite/gcc.target/riscv/movmisalign-2.c | 12 ++++++++++++
 gcc/testsuite/gcc.target/riscv/movmisalign-3.c | 12 ++++++++++++
 4 files changed, 54 insertions(+)

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 20cdb7ecfe0..5e659148403 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -1721,6 +1721,24 @@
 		      MAX_MACHINE_MODE, &operands[3], TRUE);
 })
 
+;; Misaligned (integer) moves: provide an implementation for
+;; movmisalign, so the default support_vector_misalignment() will
+;; return the right boolean depending on whether
+;; riscv_slow_unaligned_access_p is set or not.
+;;
+;; E.g., this is needed for SLP to convert "c[1] << 8) | c[0]" into a
+;; HImode load (a good test case will be blender and xalancbmk in SPEC
+;; CPU 2017).
+;;
+(define_expand "movmisalign<mode>"
+  [(set (match_operand:ANYI 0 "")
+	(match_operand:ANYI 1 ""))]
+  "!riscv_slow_unaligned_access_p"
+{
+  if (riscv_legitimize_move (<MODE>mode, operands[0], operands[1]))
+    DONE;
+})
+
 ;; 64-bit integer moves
 
 (define_expand "movdi"
diff --git a/gcc/testsuite/gcc.target/riscv/movmisalign-1.c b/gcc/testsuite/gcc.target/riscv/movmisalign-1.c
new file mode 100644
index 00000000000..791a3d63335
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movmisalign-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64 -mtune=size" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" } } */
+
+void f(unsigned short *sink, unsigned char *arr)
+{
+  *sink = (arr[1] << 8) | arr[0];
+}
+
+/* { dg-final { scan-assembler-times "lhu\t" 1 } } */
+/* { dg-final { scan-assembler-not "lbu\t" } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/movmisalign-2.c b/gcc/testsuite/gcc.target/riscv/movmisalign-2.c
new file mode 100644
index 00000000000..ef73dcb2d9d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movmisalign-2.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64 -mtune=size -mstrict-align" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" } } */
+
+void f(unsigned short *sink, unsigned char *arr)
+{
+  *sink = (arr[1] << 8) | arr[0];
+}
+
+/* { dg-final { scan-assembler-times "lbu\t" 2 } } */
+/* { dg-final { scan-assembler-not "lhu\t" } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/movmisalign-3.c b/gcc/testsuite/gcc.target/riscv/movmisalign-3.c
new file mode 100644
index 00000000000..963b11c27fd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movmisalign-3.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64 -mtune=rocket" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" } } */
+
+void f(unsigned short *sink, unsigned char *arr)
+{
+  *sink = (arr[1] << 8) | arr[0];
+}
+
+/* { dg-final { scan-assembler-times "lbu\t" 2 } } */
+/* { dg-final { scan-assembler-not "lhu\t" } } */
+

[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Implement movmisalign<mode> to enable SLP

[Philipp Tomsich]

https://gcc.gnu.org/g:34865c7b9ff35d346458a06c65d13bb1337b2196

commit 34865c7b9ff35d346458a06c65d13bb1337b2196
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date:   Wed Nov 9 12:54:32 2022 +0100

    RISC-V: Implement movmisalign<mode> to enable SLP
    
    The default implementation of support_vector_misalignment() checks
    whether movmisalign<mode> is present for the requested mode.  This
    will be used by vect_supportable_dr_alignment() to determine whether a
    misaligned access of vectorized data is permissible.
    
    For RISC-V this is required to convert multiple integer data refs,
    such as "c[1] << 8) | c[0]" into a larger (in the example before: a
    halfword load) access.
    We conditionalize on !riscv_slow_unaligned_access_p to allow the
    misaligned refs, if they are not expected to be slow.
    
    This benefits both xalancbmk and blender on SPEC CPU 2017.
    
    gcc/ChangeLog:
    
            * config/riscv/riscv.md (movmisalign<mode>): Implement.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/movmisalign-1.c: New test.
            * gcc.target/riscv/movmisalign-2.c: New test.
            * gcc.target/riscv/movmisalign-3.c: New test.
    
    Series-to: gcc-patches@gcc.gnu.org
    Series-cc: Palmer Dabbelt <palmer@rivosinc.com>
    Series-cc: Vineet Gupta <vineetg@rivosinc.com>
    Series-cc: Christoph Muellner <christoph.muellner@vrull.eu>
    Series-cc: Kito Cheng <kito.cheng@gmail.com>
    Series-cc: Jeff Law <jlaw@ventanamicro.com>

Diff:
---
 gcc/config/riscv/riscv.md                      | 18 ++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movmisalign-1.c | 12 ++++++++++++
 gcc/testsuite/gcc.target/riscv/movmisalign-2.c | 12 ++++++++++++
 gcc/testsuite/gcc.target/riscv/movmisalign-3.c | 12 ++++++++++++
 4 files changed, 54 insertions(+)

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 20cdb7ecfe0..5e659148403 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -1721,6 +1721,24 @@
 		      MAX_MACHINE_MODE, &operands[3], TRUE);
 })
 
+;; Misaligned (integer) moves: provide an implementation for
+;; movmisalign, so the default support_vector_misalignment() will
+;; return the right boolean depending on whether
+;; riscv_slow_unaligned_access_p is set or not.
+;;
+;; E.g., this is needed for SLP to convert "c[1] << 8) | c[0]" into a
+;; HImode load (a good test case will be blender and xalancbmk in SPEC
+;; CPU 2017).
+;;
+(define_expand "movmisalign<mode>"
+  [(set (match_operand:ANYI 0 "")
+	(match_operand:ANYI 1 ""))]
+  "!riscv_slow_unaligned_access_p"
+{
+  if (riscv_legitimize_move (<MODE>mode, operands[0], operands[1]))
+    DONE;
+})
+
 ;; 64-bit integer moves
 
 (define_expand "movdi"
diff --git a/gcc/testsuite/gcc.target/riscv/movmisalign-1.c b/gcc/testsuite/gcc.target/riscv/movmisalign-1.c
new file mode 100644
index 00000000000..791a3d63335
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movmisalign-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64 -mtune=size" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" } } */
+
+void f(unsigned short *sink, unsigned char *arr)
+{
+  *sink = (arr[1] << 8) | arr[0];
+}
+
+/* { dg-final { scan-assembler-times "lhu\t" 1 } } */
+/* { dg-final { scan-assembler-not "lbu\t" } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/movmisalign-2.c b/gcc/testsuite/gcc.target/riscv/movmisalign-2.c
new file mode 100644
index 00000000000..ef73dcb2d9d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movmisalign-2.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64 -mtune=size -mstrict-align" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" } } */
+
+void f(unsigned short *sink, unsigned char *arr)
+{
+  *sink = (arr[1] << 8) | arr[0];
+}
+
+/* { dg-final { scan-assembler-times "lbu\t" 2 } } */
+/* { dg-final { scan-assembler-not "lhu\t" } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/movmisalign-3.c b/gcc/testsuite/gcc.target/riscv/movmisalign-3.c
new file mode 100644
index 00000000000..963b11c27fd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movmisalign-3.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64 -mtune=rocket" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" } } */
+
+void f(unsigned short *sink, unsigned char *arr)
+{
+  *sink = (arr[1] << 8) | arr[0];
+}
+
+/* { dg-final { scan-assembler-times "lbu\t" 2 } } */
+/* { dg-final { scan-assembler-not "lhu\t" } } */
+

[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Implement movmisalign<mode> to enable SLP

[Philipp Tomsich]

https://gcc.gnu.org/g:ac8c73c8743f9cef4cde2b7db9adec79fa644ea7

commit ac8c73c8743f9cef4cde2b7db9adec79fa644ea7
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date:   Wed Nov 9 12:54:32 2022 +0100

    RISC-V: Implement movmisalign<mode> to enable SLP
    
    The default implementation of support_vector_misalignment() checks
    whether movmisalign<mode> is present for the requested mode.  This
    will be used by vect_supportable_dr_alignment() to determine whether a
    misaligned access of vectorized data is permissible.
    
    For RISC-V this is required to convert multiple integer data refs,
    such as "c[1] << 8) | c[0]" into a larger (in the example before: a
    halfword load) access.
    We conditionalize on !riscv_slow_unaligned_access_p to allow the
    misaligned refs, if they are not expected to be slow.
    
    This benefits both xalancbmk and blender on SPEC CPU 2017.
    
    gcc/ChangeLog:
    
            * config/riscv/riscv.md (movmisalign<mode>): Implement.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/movmisalign-1.c: New test.
            * gcc.target/riscv/movmisalign-2.c: New test.
            * gcc.target/riscv/movmisalign-3.c: New test.
    
    Series-to: gcc-patches@gcc.gnu.org
    Series-cc: Palmer Dabbelt <palmer@rivosinc.com>
    Series-cc: Vineet Gupta <vineetg@rivosinc.com>
    Series-cc: Christoph Muellner <christoph.muellner@vrull.eu>
    Series-cc: Kito Cheng <kito.cheng@gmail.com>
    Series-cc: Jeff Law <jlaw@ventanamicro.com>

Diff:
---
 gcc/config/riscv/riscv.md                      | 18 ++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movmisalign-1.c | 12 ++++++++++++
 gcc/testsuite/gcc.target/riscv/movmisalign-2.c | 12 ++++++++++++
 gcc/testsuite/gcc.target/riscv/movmisalign-3.c | 12 ++++++++++++
 4 files changed, 54 insertions(+)

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 20cdb7ecfe0..5e659148403 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -1721,6 +1721,24 @@
 		      MAX_MACHINE_MODE, &operands[3], TRUE);
 })
 
+;; Misaligned (integer) moves: provide an implementation for
+;; movmisalign, so the default support_vector_misalignment() will
+;; return the right boolean depending on whether
+;; riscv_slow_unaligned_access_p is set or not.
+;;
+;; E.g., this is needed for SLP to convert "c[1] << 8) | c[0]" into a
+;; HImode load (a good test case will be blender and xalancbmk in SPEC
+;; CPU 2017).
+;;
+(define_expand "movmisalign<mode>"
+  [(set (match_operand:ANYI 0 "")
+	(match_operand:ANYI 1 ""))]
+  "!riscv_slow_unaligned_access_p"
+{
+  if (riscv_legitimize_move (<MODE>mode, operands[0], operands[1]))
+    DONE;
+})
+
 ;; 64-bit integer moves
 
 (define_expand "movdi"
diff --git a/gcc/testsuite/gcc.target/riscv/movmisalign-1.c b/gcc/testsuite/gcc.target/riscv/movmisalign-1.c
new file mode 100644
index 00000000000..791a3d63335
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movmisalign-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64 -mtune=size" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" } } */
+
+void f(unsigned short *sink, unsigned char *arr)
+{
+  *sink = (arr[1] << 8) | arr[0];
+}
+
+/* { dg-final { scan-assembler-times "lhu\t" 1 } } */
+/* { dg-final { scan-assembler-not "lbu\t" } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/movmisalign-2.c b/gcc/testsuite/gcc.target/riscv/movmisalign-2.c
new file mode 100644
index 00000000000..ef73dcb2d9d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movmisalign-2.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64 -mtune=size -mstrict-align" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" } } */
+
+void f(unsigned short *sink, unsigned char *arr)
+{
+  *sink = (arr[1] << 8) | arr[0];
+}
+
+/* { dg-final { scan-assembler-times "lbu\t" 2 } } */
+/* { dg-final { scan-assembler-not "lhu\t" } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/movmisalign-3.c b/gcc/testsuite/gcc.target/riscv/movmisalign-3.c
new file mode 100644
index 00000000000..963b11c27fd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movmisalign-3.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64 -mtune=rocket" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" } } */
+
+void f(unsigned short *sink, unsigned char *arr)
+{
+  *sink = (arr[1] << 8) | arr[0];
+}
+
+/* { dg-final { scan-assembler-times "lbu\t" 2 } } */
+/* { dg-final { scan-assembler-not "lhu\t" } } */
+