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* [gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Recognize xventanacondops extension
@ 2022-11-15 14:01 Philipp Tomsich
  0 siblings, 0 replies; 6+ messages in thread
From: Philipp Tomsich @ 2022-11-15 14:01 UTC (permalink / raw)
  To: gcc-cvs

https://gcc.gnu.org/g:92e56034fecb997cbf330e7e5d0ae2785e818678

commit 92e56034fecb997cbf330e7e5d0ae2785e818678
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date:   Sat Mar 5 23:19:03 2022 +0100

    RISC-V: Recognize xventanacondops extension
    
    This adds the xventanacondops extension to the option parsing and as a
    default for the ventana-vt1 core:
    
    gcc/Changelog:
    
            * common/config/riscv/riscv-common.cc: Recognize
              "xventanacondops" as part of an architecture string.
            * config/riscv/riscv-opts.h (MASK_XVENTANACONDOPS): Define.
            (TARGET_XVENTANACONDOPS): Define.
            * config/riscv/riscv.opt: Add "riscv_xventanacondops".
    
    Cover-letter:
    RISC-V: Backend support for XVentanaCondOps/ZiCondops
    
    Both the XVentanaCondOps (a vendor-defined extension from Ventana
    Microsystems) and the proposed ZiCondOps extensions define a
    conditional-zero(-or-value) instruction, which is similar to the
    following C construct:
      rd = rc ? rs : 0
    
    This functionality can be tied back into if-convertsion and also match
    some typical programming idioms.  This series includes backend support
    for XVentanaCondops and infrastructure to handle conditional-zero
    constructions in if-conversion.
    
    Tested against SPEC CPU 2017.
    
    END
    
    Series-to: gcc-patches@gcc.gnu.org
    Series-cc: Palmer Dabbelt <palmer@rivosinc.com>
    Series-cc: Vineet Gupta <vineetg@rivosinc.com>
    Series-cc: Christoph Muellner <christoph.muellner@vrull.eu>
    Series-cc: Kito Cheng <kito.cheng@gmail.com>
    Series-cc: Jeff Law <jlaw@ventanamicro.com>
    
    Series-version: 3
    Series-changes: 2
    - Restore a (during rebase) dropped line to xventanacondops.md
    - Include the change to add xventanacondops to the VT1 code definition]
      as a separate patch.
    
    Series-changes: 3
    - Address missed opportunities for forming CondOps.

Diff:
---
 gcc/common/config/riscv/riscv-common.cc | 2 ++
 gcc/config/riscv/riscv-opts.h           | 3 +++
 gcc/config/riscv/riscv.opt              | 3 +++
 3 files changed, 8 insertions(+)

diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index 4b7f777c103..6b2bdda5feb 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -1247,6 +1247,8 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
   {"svinval", &gcc_options::x_riscv_sv_subext, MASK_SVINVAL},
   {"svnapot", &gcc_options::x_riscv_sv_subext, MASK_SVNAPOT},
 
+  {"xventanacondops", &gcc_options::x_riscv_xventanacondops, MASK_XVENTANACONDOPS},
+
   {NULL, NULL, 0}
 };
 
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 25fd85b09b1..84c987626bc 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -189,4 +189,7 @@ enum stack_protector_guard {
    ? 0 \
    : 32 << (__builtin_popcount (riscv_zvl_flags) - 1))
 
+#define MASK_XVENTANACONDOPS (1 << 0)
+#define TARGET_XVENTANACONDOPS ((riscv_xventanacondops & MASK_XVENTANACONDOPS) != 0)
+
 #endif /* ! GCC_RISCV_OPTS_H */
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 7c3ca48d1cc..9595078bdd4 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -233,6 +233,9 @@ int riscv_zm_subext
 TargetVariable
 int riscv_sv_subext
 
+TargetVariable
+int riscv_xventanacondops = 0
+
 Enum
 Name(isa_spec_class) Type(enum riscv_isa_spec_class)
 Supported ISA specs (for use with the -misa-spec= option):

^ permalink raw reply	[flat|nested] 6+ messages in thread
* [gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Recognize xventanacondops extension
@ 2022-12-01 13:23 Philipp Tomsich
  0 siblings, 0 replies; 6+ messages in thread
From: Philipp Tomsich @ 2022-12-01 13:23 UTC (permalink / raw)
  To: gcc-cvs

https://gcc.gnu.org/g:7684dea9c91a69008bc270f74f5db47b24ebad3c

commit 7684dea9c91a69008bc270f74f5db47b24ebad3c
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date:   Sat Mar 5 23:19:03 2022 +0100

    RISC-V: Recognize xventanacondops extension
    
    This adds the xventanacondops extension to the option parsing and as a
    default for the ventana-vt1 core:
    
    gcc/Changelog:
    
            * common/config/riscv/riscv-common.cc: Recognize
              "xventanacondops" as part of an architecture string.
            * config/riscv/riscv-opts.h (MASK_XVENTANACONDOPS): Define.
            (TARGET_XVENTANACONDOPS): Define.
            * config/riscv/riscv.opt: Add "riscv_xventanacondops".
    
    Cover-letter:
    RISC-V: Backend support for XVentanaCondOps/ZiCondops
    
    Both the XVentanaCondOps (a vendor-defined extension from Ventana
    Microsystems) and the proposed ZiCondOps extensions define a
    conditional-zero(-or-value) instruction, which is similar to the
    following C construct:
      rd = rc ? rs : 0
    
    This functionality can be tied back into if-convertsion and also match
    some typical programming idioms.  This series includes backend support
    for XVentanaCondops and infrastructure to handle conditional-zero
    constructions in if-conversion.
    
    Tested against SPEC CPU 2017.
    
    END
    
    Series-to: gcc-patches@gcc.gnu.org
    Series-cc: Palmer Dabbelt <palmer@rivosinc.com>
    Series-cc: Vineet Gupta <vineetg@rivosinc.com>
    Series-cc: Christoph Muellner <christoph.muellner@vrull.eu>
    Series-cc: Kito Cheng <kito.cheng@gmail.com>
    Series-cc: Jeff Law <jlaw@ventanamicro.com>
    
    Series-version: 4
    Series-changes: 2
    - Restore a (during rebase) dropped line to xventanacondops.md
    - Include the change to add xventanacondops to the VT1 code definition]
      as a separate patch.
    
    Series-changes: 3
    - Address missed opportunities for forming CondOps.
    
    Series-changes: 4
    - Address a code-generation issue for non-XVentanaCondOps targets (in
      ifcvt) caused by a modification to if_info despite try_condzero
      failing.

Diff:
---
 gcc/common/config/riscv/riscv-common.cc | 2 ++
 gcc/config/riscv/riscv-opts.h           | 3 +++
 gcc/config/riscv/riscv.opt              | 3 +++
 3 files changed, 8 insertions(+)

diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index 4b7f777c103..6b2bdda5feb 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -1247,6 +1247,8 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
   {"svinval", &gcc_options::x_riscv_sv_subext, MASK_SVINVAL},
   {"svnapot", &gcc_options::x_riscv_sv_subext, MASK_SVNAPOT},
 
+  {"xventanacondops", &gcc_options::x_riscv_xventanacondops, MASK_XVENTANACONDOPS},
+
   {NULL, NULL, 0}
 };
 
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 25fd85b09b1..84c987626bc 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -189,4 +189,7 @@ enum stack_protector_guard {
    ? 0 \
    : 32 << (__builtin_popcount (riscv_zvl_flags) - 1))
 
+#define MASK_XVENTANACONDOPS (1 << 0)
+#define TARGET_XVENTANACONDOPS ((riscv_xventanacondops & MASK_XVENTANACONDOPS) != 0)
+
 #endif /* ! GCC_RISCV_OPTS_H */
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 7c3ca48d1cc..9595078bdd4 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -233,6 +233,9 @@ int riscv_zm_subext
 TargetVariable
 int riscv_sv_subext
 
+TargetVariable
+int riscv_xventanacondops = 0
+
 Enum
 Name(isa_spec_class) Type(enum riscv_isa_spec_class)
 Supported ISA specs (for use with the -misa-spec= option):

^ permalink raw reply	[flat|nested] 6+ messages in thread
* [gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Recognize xventanacondops extension
@ 2022-11-18 20:25 Philipp Tomsich
  0 siblings, 0 replies; 6+ messages in thread
From: Philipp Tomsich @ 2022-11-18 20:25 UTC (permalink / raw)
  To: gcc-cvs

https://gcc.gnu.org/g:d7568dade1cdc29b6ec9f77adf557c90996512ff

commit d7568dade1cdc29b6ec9f77adf557c90996512ff
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date:   Sat Mar 5 23:19:03 2022 +0100

    RISC-V: Recognize xventanacondops extension
    
    This adds the xventanacondops extension to the option parsing and as a
    default for the ventana-vt1 core:
    
    gcc/Changelog:
    
            * common/config/riscv/riscv-common.cc: Recognize
              "xventanacondops" as part of an architecture string.
            * config/riscv/riscv-opts.h (MASK_XVENTANACONDOPS): Define.
            (TARGET_XVENTANACONDOPS): Define.
            * config/riscv/riscv.opt: Add "riscv_xventanacondops".
    
    Cover-letter:
    RISC-V: Backend support for XVentanaCondOps/ZiCondops
    
    Both the XVentanaCondOps (a vendor-defined extension from Ventana
    Microsystems) and the proposed ZiCondOps extensions define a
    conditional-zero(-or-value) instruction, which is similar to the
    following C construct:
      rd = rc ? rs : 0
    
    This functionality can be tied back into if-convertsion and also match
    some typical programming idioms.  This series includes backend support
    for XVentanaCondops and infrastructure to handle conditional-zero
    constructions in if-conversion.
    
    Tested against SPEC CPU 2017.
    
    END
    
    Series-to: gcc-patches@gcc.gnu.org
    Series-cc: Palmer Dabbelt <palmer@rivosinc.com>
    Series-cc: Vineet Gupta <vineetg@rivosinc.com>
    Series-cc: Christoph Muellner <christoph.muellner@vrull.eu>
    Series-cc: Kito Cheng <kito.cheng@gmail.com>
    Series-cc: Jeff Law <jlaw@ventanamicro.com>
    
    Series-version: 3
    Series-changes: 2
    - Restore a (during rebase) dropped line to xventanacondops.md
    - Include the change to add xventanacondops to the VT1 code definition]
      as a separate patch.
    
    Series-changes: 3
    - Address missed opportunities for forming CondOps.

Diff:
---
 gcc/common/config/riscv/riscv-common.cc | 2 ++
 gcc/config/riscv/riscv-opts.h           | 3 +++
 gcc/config/riscv/riscv.opt              | 3 +++
 3 files changed, 8 insertions(+)

diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index 4b7f777c103..6b2bdda5feb 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -1247,6 +1247,8 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
   {"svinval", &gcc_options::x_riscv_sv_subext, MASK_SVINVAL},
   {"svnapot", &gcc_options::x_riscv_sv_subext, MASK_SVNAPOT},
 
+  {"xventanacondops", &gcc_options::x_riscv_xventanacondops, MASK_XVENTANACONDOPS},
+
   {NULL, NULL, 0}
 };
 
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 25fd85b09b1..84c987626bc 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -189,4 +189,7 @@ enum stack_protector_guard {
    ? 0 \
    : 32 << (__builtin_popcount (riscv_zvl_flags) - 1))
 
+#define MASK_XVENTANACONDOPS (1 << 0)
+#define TARGET_XVENTANACONDOPS ((riscv_xventanacondops & MASK_XVENTANACONDOPS) != 0)
+
 #endif /* ! GCC_RISCV_OPTS_H */
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 7c3ca48d1cc..9595078bdd4 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -233,6 +233,9 @@ int riscv_zm_subext
 TargetVariable
 int riscv_sv_subext
 
+TargetVariable
+int riscv_xventanacondops = 0
+
 Enum
 Name(isa_spec_class) Type(enum riscv_isa_spec_class)
 Supported ISA specs (for use with the -misa-spec= option):

^ permalink raw reply	[flat|nested] 6+ messages in thread
* [gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Recognize xventanacondops extension
@ 2022-11-18 20:22 Philipp Tomsich
  0 siblings, 0 replies; 6+ messages in thread
From: Philipp Tomsich @ 2022-11-18 20:22 UTC (permalink / raw)
  To: gcc-cvs

https://gcc.gnu.org/g:9ef7c58fa23a2a995f67ea45b2d5d028e2a0dd27

commit 9ef7c58fa23a2a995f67ea45b2d5d028e2a0dd27
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date:   Sat Mar 5 23:19:03 2022 +0100

    RISC-V: Recognize xventanacondops extension
    
    This adds the xventanacondops extension to the option parsing and as a
    default for the ventana-vt1 core:
    
    gcc/Changelog:
    
            * common/config/riscv/riscv-common.cc: Recognize
              "xventanacondops" as part of an architecture string.
            * config/riscv/riscv-opts.h (MASK_XVENTANACONDOPS): Define.
            (TARGET_XVENTANACONDOPS): Define.
            * config/riscv/riscv.opt: Add "riscv_xventanacondops".
    
    Cover-letter:
    RISC-V: Backend support for XVentanaCondOps/ZiCondops
    
    Both the XVentanaCondOps (a vendor-defined extension from Ventana
    Microsystems) and the proposed ZiCondOps extensions define a
    conditional-zero(-or-value) instruction, which is similar to the
    following C construct:
      rd = rc ? rs : 0
    
    This functionality can be tied back into if-convertsion and also match
    some typical programming idioms.  This series includes backend support
    for XVentanaCondops and infrastructure to handle conditional-zero
    constructions in if-conversion.
    
    Tested against SPEC CPU 2017.
    
    END
    
    Series-to: gcc-patches@gcc.gnu.org
    Series-cc: Palmer Dabbelt <palmer@rivosinc.com>
    Series-cc: Vineet Gupta <vineetg@rivosinc.com>
    Series-cc: Christoph Muellner <christoph.muellner@vrull.eu>
    Series-cc: Kito Cheng <kito.cheng@gmail.com>
    Series-cc: Jeff Law <jlaw@ventanamicro.com>
    
    Series-version: 3
    Series-changes: 2
    - Restore a (during rebase) dropped line to xventanacondops.md
    - Include the change to add xventanacondops to the VT1 code definition]
      as a separate patch.
    
    Series-changes: 3
    - Address missed opportunities for forming CondOps.

Diff:
---
 gcc/common/config/riscv/riscv-common.cc | 2 ++
 gcc/config/riscv/riscv-opts.h           | 3 +++
 gcc/config/riscv/riscv.opt              | 3 +++
 3 files changed, 8 insertions(+)

diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index 4b7f777c103..6b2bdda5feb 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -1247,6 +1247,8 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
   {"svinval", &gcc_options::x_riscv_sv_subext, MASK_SVINVAL},
   {"svnapot", &gcc_options::x_riscv_sv_subext, MASK_SVNAPOT},
 
+  {"xventanacondops", &gcc_options::x_riscv_xventanacondops, MASK_XVENTANACONDOPS},
+
   {NULL, NULL, 0}
 };
 
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 25fd85b09b1..84c987626bc 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -189,4 +189,7 @@ enum stack_protector_guard {
    ? 0 \
    : 32 << (__builtin_popcount (riscv_zvl_flags) - 1))
 
+#define MASK_XVENTANACONDOPS (1 << 0)
+#define TARGET_XVENTANACONDOPS ((riscv_xventanacondops & MASK_XVENTANACONDOPS) != 0)
+
 #endif /* ! GCC_RISCV_OPTS_H */
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 7c3ca48d1cc..9595078bdd4 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -233,6 +233,9 @@ int riscv_zm_subext
 TargetVariable
 int riscv_sv_subext
 
+TargetVariable
+int riscv_xventanacondops = 0
+
 Enum
 Name(isa_spec_class) Type(enum riscv_isa_spec_class)
 Supported ISA specs (for use with the -misa-spec= option):

^ permalink raw reply	[flat|nested] 6+ messages in thread
* [gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Recognize xventanacondops extension
@ 2022-11-18 11:35 Philipp Tomsich
  0 siblings, 0 replies; 6+ messages in thread
From: Philipp Tomsich @ 2022-11-18 11:35 UTC (permalink / raw)
  To: gcc-cvs

https://gcc.gnu.org/g:ea64d454846fff9d7a4e0835ff6a8e68a5b15768

commit ea64d454846fff9d7a4e0835ff6a8e68a5b15768
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date:   Sat Mar 5 23:19:03 2022 +0100

    RISC-V: Recognize xventanacondops extension
    
    This adds the xventanacondops extension to the option parsing and as a
    default for the ventana-vt1 core:
    
    gcc/Changelog:
    
            * common/config/riscv/riscv-common.cc: Recognize
              "xventanacondops" as part of an architecture string.
            * config/riscv/riscv-opts.h (MASK_XVENTANACONDOPS): Define.
            (TARGET_XVENTANACONDOPS): Define.
            * config/riscv/riscv.opt: Add "riscv_xventanacondops".
    
    Cover-letter:
    RISC-V: Backend support for XVentanaCondOps/ZiCondops
    
    Both the XVentanaCondOps (a vendor-defined extension from Ventana
    Microsystems) and the proposed ZiCondOps extensions define a
    conditional-zero(-or-value) instruction, which is similar to the
    following C construct:
      rd = rc ? rs : 0
    
    This functionality can be tied back into if-convertsion and also match
    some typical programming idioms.  This series includes backend support
    for XVentanaCondops and infrastructure to handle conditional-zero
    constructions in if-conversion.
    
    Tested against SPEC CPU 2017.
    
    END
    
    Series-to: gcc-patches@gcc.gnu.org
    Series-cc: Palmer Dabbelt <palmer@rivosinc.com>
    Series-cc: Vineet Gupta <vineetg@rivosinc.com>
    Series-cc: Christoph Muellner <christoph.muellner@vrull.eu>
    Series-cc: Kito Cheng <kito.cheng@gmail.com>
    Series-cc: Jeff Law <jlaw@ventanamicro.com>
    
    Series-version: 3
    Series-changes: 2
    - Restore a (during rebase) dropped line to xventanacondops.md
    - Include the change to add xventanacondops to the VT1 code definition]
      as a separate patch.
    
    Series-changes: 3
    - Address missed opportunities for forming CondOps.

Diff:
---
 gcc/common/config/riscv/riscv-common.cc | 2 ++
 gcc/config/riscv/riscv-opts.h           | 3 +++
 gcc/config/riscv/riscv.opt              | 3 +++
 3 files changed, 8 insertions(+)

diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index 4b7f777c103..6b2bdda5feb 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -1247,6 +1247,8 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
   {"svinval", &gcc_options::x_riscv_sv_subext, MASK_SVINVAL},
   {"svnapot", &gcc_options::x_riscv_sv_subext, MASK_SVNAPOT},
 
+  {"xventanacondops", &gcc_options::x_riscv_xventanacondops, MASK_XVENTANACONDOPS},
+
   {NULL, NULL, 0}
 };
 
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 25fd85b09b1..84c987626bc 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -189,4 +189,7 @@ enum stack_protector_guard {
    ? 0 \
    : 32 << (__builtin_popcount (riscv_zvl_flags) - 1))
 
+#define MASK_XVENTANACONDOPS (1 << 0)
+#define TARGET_XVENTANACONDOPS ((riscv_xventanacondops & MASK_XVENTANACONDOPS) != 0)
+
 #endif /* ! GCC_RISCV_OPTS_H */
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 7c3ca48d1cc..9595078bdd4 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -233,6 +233,9 @@ int riscv_zm_subext
 TargetVariable
 int riscv_sv_subext
 
+TargetVariable
+int riscv_xventanacondops = 0
+
 Enum
 Name(isa_spec_class) Type(enum riscv_isa_spec_class)
 Supported ISA specs (for use with the -misa-spec= option):

^ permalink raw reply	[flat|nested] 6+ messages in thread
* [gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Recognize xventanacondops extension
@ 2022-11-17 22:25 Philipp Tomsich
  0 siblings, 0 replies; 6+ messages in thread
From: Philipp Tomsich @ 2022-11-17 22:25 UTC (permalink / raw)
  To: gcc-cvs

https://gcc.gnu.org/g:830289f3c63df1213adb4d6772d91fdc20e7aecd

commit 830289f3c63df1213adb4d6772d91fdc20e7aecd
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date:   Sat Mar 5 23:19:03 2022 +0100

    RISC-V: Recognize xventanacondops extension
    
    This adds the xventanacondops extension to the option parsing and as a
    default for the ventana-vt1 core:
    
    gcc/Changelog:
    
            * common/config/riscv/riscv-common.cc: Recognize
              "xventanacondops" as part of an architecture string.
            * config/riscv/riscv-opts.h (MASK_XVENTANACONDOPS): Define.
            (TARGET_XVENTANACONDOPS): Define.
            * config/riscv/riscv.opt: Add "riscv_xventanacondops".
    
    Cover-letter:
    RISC-V: Backend support for XVentanaCondOps/ZiCondops
    
    Both the XVentanaCondOps (a vendor-defined extension from Ventana
    Microsystems) and the proposed ZiCondOps extensions define a
    conditional-zero(-or-value) instruction, which is similar to the
    following C construct:
      rd = rc ? rs : 0
    
    This functionality can be tied back into if-convertsion and also match
    some typical programming idioms.  This series includes backend support
    for XVentanaCondops and infrastructure to handle conditional-zero
    constructions in if-conversion.
    
    Tested against SPEC CPU 2017.
    
    END
    
    Series-to: gcc-patches@gcc.gnu.org
    Series-cc: Palmer Dabbelt <palmer@rivosinc.com>
    Series-cc: Vineet Gupta <vineetg@rivosinc.com>
    Series-cc: Christoph Muellner <christoph.muellner@vrull.eu>
    Series-cc: Kito Cheng <kito.cheng@gmail.com>
    Series-cc: Jeff Law <jlaw@ventanamicro.com>
    
    Series-version: 3
    Series-changes: 2
    - Restore a (during rebase) dropped line to xventanacondops.md
    - Include the change to add xventanacondops to the VT1 code definition]
      as a separate patch.
    
    Series-changes: 3
    - Address missed opportunities for forming CondOps.

Diff:
---
 gcc/common/config/riscv/riscv-common.cc | 2 ++
 gcc/config/riscv/riscv-opts.h           | 3 +++
 gcc/config/riscv/riscv.opt              | 3 +++
 3 files changed, 8 insertions(+)

diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index 4b7f777c103..6b2bdda5feb 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -1247,6 +1247,8 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
   {"svinval", &gcc_options::x_riscv_sv_subext, MASK_SVINVAL},
   {"svnapot", &gcc_options::x_riscv_sv_subext, MASK_SVNAPOT},
 
+  {"xventanacondops", &gcc_options::x_riscv_xventanacondops, MASK_XVENTANACONDOPS},
+
   {NULL, NULL, 0}
 };
 
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 25fd85b09b1..84c987626bc 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -189,4 +189,7 @@ enum stack_protector_guard {
    ? 0 \
    : 32 << (__builtin_popcount (riscv_zvl_flags) - 1))
 
+#define MASK_XVENTANACONDOPS (1 << 0)
+#define TARGET_XVENTANACONDOPS ((riscv_xventanacondops & MASK_XVENTANACONDOPS) != 0)
+
 #endif /* ! GCC_RISCV_OPTS_H */
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 7c3ca48d1cc..9595078bdd4 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -233,6 +233,9 @@ int riscv_zm_subext
 TargetVariable
 int riscv_sv_subext
 
+TargetVariable
+int riscv_xventanacondops = 0
+
 Enum
 Name(isa_spec_class) Type(enum riscv_isa_spec_class)
 Supported ISA specs (for use with the -misa-spec= option):

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