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* [gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Generate vt.maskc<n> on noce_try_store_flag_mask if-conversion
@ 2022-11-15 14:01 Philipp Tomsich
0 siblings, 0 replies; 6+ messages in thread
From: Philipp Tomsich @ 2022-11-15 14:01 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:6ae6ae2313982652f008ea2875322efe5fb22f7c
commit 6ae6ae2313982652f008ea2875322efe5fb22f7c
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date: Sat Mar 5 23:21:10 2022 +0100
RISC-V: Generate vt.maskc<n> on noce_try_store_flag_mask if-conversion
Adds a pattern to map the output of noce_try_store_flag_mask
if-conversion in the combiner onto vt.maskc<n>; the input patterns
supported are similar to the following:
(set (reg/v/f:DI 75 [ <retval> ])
(and:DI (neg:DI (ne:DI (reg:DI 82)
(const_int 0 [0])))
(reg/v/f:DI 75 [ <retval> ])))
This reduces dynamic instruction counts for the perlbench-workload in
SPEC CPU2017 by 0.8230%, 0.4689%, and 0.2332% (respectively, for the
each of the 3 workloads in the 'ref'-workload).
To ensure that the combine-pass doesn't get confused about
profitability, we recognize the idiom as requiring a single
instruction when the XVentanaCondOps extension is present.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_rtx_costs): Recognize idiom for
vt.maskc<n> as a single insn with TARGET_XVENTANACONDOPS.
* config/riscv/riscv.md: Include xventanacondops.md.
* config/riscv/xventanacondops.md: New file.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/xventanacondops-ne-03.c: New test.
* gcc.target/riscv/xventanacondops-ne-04.c: New test.
Commit-changes: 2
- Ran whitespace-cleanup on xventanacondops-ne-03.c
- Ran whitespace-cleanup on xventanacondops-ne-04.c
Diff:
---
gcc/config/riscv/riscv.cc | 14 ++++++++++
gcc/config/riscv/riscv.md | 1 +
gcc/config/riscv/xventanacondops.md | 30 ++++++++++++++++++++++
.../gcc.target/riscv/xventanacondops-ne-03.c | 13 ++++++++++
.../gcc.target/riscv/xventanacondops-ne-04.c | 13 ++++++++++
5 files changed, 71 insertions(+)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 451ec7034c6..c04e5db21df 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -2300,6 +2300,20 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
return false;
case AND:
+ /* vt.maskc/vt.maskcn for XVentanaCondOps */
+ if (TARGET_XVENTANACONDOPS && mode == word_mode
+ && GET_CODE (XEXP (x, 0)) == NEG)
+ {
+ rtx inner = XEXP (XEXP (x, 0), 0);
+
+ if ((GET_CODE (inner) == EQ || GET_CODE (inner) == NE)
+ && CONST_INT_P (XEXP (inner, 1))
+ && INTVAL (XEXP (inner, 1)) == 0)
+ {
+ *total = COSTS_N_INSNS (1);
+ return true;
+ }
+ }
/* slli.uw pattern for zba. */
if (TARGET_ZBA && TARGET_64BIT && mode == DImode
&& GET_CODE (XEXP (x, 0)) == ASHIFT)
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 7529987201c..a1b51f93c21 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -3199,3 +3199,4 @@
(include "generic.md")
(include "sifive-7.md")
(include "vector.md")
+(include "xventanacondops.md")
diff --git a/gcc/config/riscv/xventanacondops.md b/gcc/config/riscv/xventanacondops.md
new file mode 100644
index 00000000000..641cef0e44e
--- /dev/null
+++ b/gcc/config/riscv/xventanacondops.md
@@ -0,0 +1,30 @@
+;; Machine description for X-Ventana-CondOps
+;; Copyright (C) 2022 Free Software Foundation, Inc.
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3. If not see
+;; <http://www.gnu.org/licenses/>.
+
+(define_code_iterator eq_or_ne [eq ne])
+(define_code_attr n [(eq "n") (ne "")])
+
+(define_insn "*vt.maskc<n>"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (and:DI (neg:DI (eq_or_ne:DI
+ (match_operand:DI 1 "register_operand" "r")
+ (const_int 0)))
+ (match_operand:DI 2 "register_operand" "r")))]
+ "TARGET_XVENTANACONDOPS"
+ "vt.maskc<n>\t%0,%2,%1")
diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-03.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-03.c
new file mode 100644
index 00000000000..4a762a1ed61
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-03.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64 -mtune=thead-c906" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" "-Os" "-Oz" } } */
+
+long long ne3(long long a, long long b)
+{
+ if (a != 0)
+ return b;
+
+ return 0;
+}
+
+/* { dg-final { scan-assembler-times "vt.maskc" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-04.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-04.c
new file mode 100644
index 00000000000..18b35ac7070
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-04.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64 -mtune=thead-c906" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+
+long long ne4(long long a, long long b)
+{
+ if (a != 0)
+ return 0;
+
+ return b;
+}
+
+/* { dg-final { scan-assembler-times "vt.maskcn" 1 } } */
^ permalink raw reply [flat|nested] 6+ messages in thread
* [gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Generate vt.maskc<n> on noce_try_store_flag_mask if-conversion
@ 2022-12-01 13:23 Philipp Tomsich
0 siblings, 0 replies; 6+ messages in thread
From: Philipp Tomsich @ 2022-12-01 13:23 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:efee69b0eec53614f6360ceeaf60d4c886b2ce6e
commit efee69b0eec53614f6360ceeaf60d4c886b2ce6e
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date: Sat Mar 5 23:21:10 2022 +0100
RISC-V: Generate vt.maskc<n> on noce_try_store_flag_mask if-conversion
Adds a pattern to map the output of noce_try_store_flag_mask
if-conversion in the combiner onto vt.maskc<n>; the input patterns
supported are similar to the following:
(set (reg/v/f:DI 75 [ <retval> ])
(and:DI (neg:DI (ne:DI (reg:DI 82)
(const_int 0 [0])))
(reg/v/f:DI 75 [ <retval> ])))
This reduces dynamic instruction counts for the perlbench-workload in
SPEC CPU2017 by 0.8230%, 0.4689%, and 0.2332% (respectively, for the
each of the 3 workloads in the 'ref'-workload).
To ensure that the combine-pass doesn't get confused about
profitability, we recognize the idiom as requiring a single
instruction when the XVentanaCondOps extension is present.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_rtx_costs): Recognize idiom for
vt.maskc<n> as a single insn with TARGET_XVENTANACONDOPS.
* config/riscv/riscv.md: Include xventanacondops.md.
* config/riscv/xventanacondops.md: New file.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/xventanacondops-ne-03.c: New test.
* gcc.target/riscv/xventanacondops-ne-04.c: New test.
Commit-changes: 2
- Ran whitespace-cleanup on xventanacondops-ne-03.c
- Ran whitespace-cleanup on xventanacondops-ne-04.c
Diff:
---
gcc/config/riscv/riscv.cc | 14 ++++++++++
gcc/config/riscv/riscv.md | 1 +
gcc/config/riscv/xventanacondops.md | 30 ++++++++++++++++++++++
.../gcc.target/riscv/xventanacondops-ne-03.c | 13 ++++++++++
.../gcc.target/riscv/xventanacondops-ne-04.c | 13 ++++++++++
5 files changed, 71 insertions(+)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 9a4dad40193..1e82b743c15 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -2307,6 +2307,20 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
return false;
case AND:
+ /* vt.maskc/vt.maskcn for XVentanaCondOps */
+ if (TARGET_XVENTANACONDOPS && mode == word_mode
+ && GET_CODE (XEXP (x, 0)) == NEG)
+ {
+ rtx inner = XEXP (XEXP (x, 0), 0);
+
+ if ((GET_CODE (inner) == EQ || GET_CODE (inner) == NE)
+ && CONST_INT_P (XEXP (inner, 1))
+ && INTVAL (XEXP (inner, 1)) == 0)
+ {
+ *total = COSTS_N_INSNS (1);
+ return true;
+ }
+ }
/* slli.uw pattern for zba. */
if (TARGET_ZBA && TARGET_64BIT && mode == DImode
&& GET_CODE (XEXP (x, 0)) == ASHIFT)
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 328e139705a..14db75faccd 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -3207,3 +3207,4 @@
(include "generic.md")
(include "sifive-7.md")
(include "vector.md")
+(include "xventanacondops.md")
diff --git a/gcc/config/riscv/xventanacondops.md b/gcc/config/riscv/xventanacondops.md
new file mode 100644
index 00000000000..641cef0e44e
--- /dev/null
+++ b/gcc/config/riscv/xventanacondops.md
@@ -0,0 +1,30 @@
+;; Machine description for X-Ventana-CondOps
+;; Copyright (C) 2022 Free Software Foundation, Inc.
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3. If not see
+;; <http://www.gnu.org/licenses/>.
+
+(define_code_iterator eq_or_ne [eq ne])
+(define_code_attr n [(eq "n") (ne "")])
+
+(define_insn "*vt.maskc<n>"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (and:DI (neg:DI (eq_or_ne:DI
+ (match_operand:DI 1 "register_operand" "r")
+ (const_int 0)))
+ (match_operand:DI 2 "register_operand" "r")))]
+ "TARGET_XVENTANACONDOPS"
+ "vt.maskc<n>\t%0,%2,%1")
diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-03.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-03.c
new file mode 100644
index 00000000000..4a762a1ed61
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-03.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64 -mtune=thead-c906" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" "-Os" "-Oz" } } */
+
+long long ne3(long long a, long long b)
+{
+ if (a != 0)
+ return b;
+
+ return 0;
+}
+
+/* { dg-final { scan-assembler-times "vt.maskc" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-04.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-04.c
new file mode 100644
index 00000000000..18b35ac7070
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-04.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64 -mtune=thead-c906" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+
+long long ne4(long long a, long long b)
+{
+ if (a != 0)
+ return 0;
+
+ return b;
+}
+
+/* { dg-final { scan-assembler-times "vt.maskcn" 1 } } */
^ permalink raw reply [flat|nested] 6+ messages in thread
* [gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Generate vt.maskc<n> on noce_try_store_flag_mask if-conversion
@ 2022-11-18 20:25 Philipp Tomsich
0 siblings, 0 replies; 6+ messages in thread
From: Philipp Tomsich @ 2022-11-18 20:25 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:01d23996aa6393f24c353bae9da391b40d4a694b
commit 01d23996aa6393f24c353bae9da391b40d4a694b
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date: Sat Mar 5 23:21:10 2022 +0100
RISC-V: Generate vt.maskc<n> on noce_try_store_flag_mask if-conversion
Adds a pattern to map the output of noce_try_store_flag_mask
if-conversion in the combiner onto vt.maskc<n>; the input patterns
supported are similar to the following:
(set (reg/v/f:DI 75 [ <retval> ])
(and:DI (neg:DI (ne:DI (reg:DI 82)
(const_int 0 [0])))
(reg/v/f:DI 75 [ <retval> ])))
This reduces dynamic instruction counts for the perlbench-workload in
SPEC CPU2017 by 0.8230%, 0.4689%, and 0.2332% (respectively, for the
each of the 3 workloads in the 'ref'-workload).
To ensure that the combine-pass doesn't get confused about
profitability, we recognize the idiom as requiring a single
instruction when the XVentanaCondOps extension is present.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_rtx_costs): Recognize idiom for
vt.maskc<n> as a single insn with TARGET_XVENTANACONDOPS.
* config/riscv/riscv.md: Include xventanacondops.md.
* config/riscv/xventanacondops.md: New file.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/xventanacondops-ne-03.c: New test.
* gcc.target/riscv/xventanacondops-ne-04.c: New test.
Commit-changes: 2
- Ran whitespace-cleanup on xventanacondops-ne-03.c
- Ran whitespace-cleanup on xventanacondops-ne-04.c
Diff:
---
gcc/config/riscv/riscv.cc | 14 ++++++++++
gcc/config/riscv/riscv.md | 1 +
gcc/config/riscv/xventanacondops.md | 30 ++++++++++++++++++++++
.../gcc.target/riscv/xventanacondops-ne-03.c | 13 ++++++++++
.../gcc.target/riscv/xventanacondops-ne-04.c | 13 ++++++++++
5 files changed, 71 insertions(+)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 9a4dad40193..1e82b743c15 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -2307,6 +2307,20 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
return false;
case AND:
+ /* vt.maskc/vt.maskcn for XVentanaCondOps */
+ if (TARGET_XVENTANACONDOPS && mode == word_mode
+ && GET_CODE (XEXP (x, 0)) == NEG)
+ {
+ rtx inner = XEXP (XEXP (x, 0), 0);
+
+ if ((GET_CODE (inner) == EQ || GET_CODE (inner) == NE)
+ && CONST_INT_P (XEXP (inner, 1))
+ && INTVAL (XEXP (inner, 1)) == 0)
+ {
+ *total = COSTS_N_INSNS (1);
+ return true;
+ }
+ }
/* slli.uw pattern for zba. */
if (TARGET_ZBA && TARGET_64BIT && mode == DImode
&& GET_CODE (XEXP (x, 0)) == ASHIFT)
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 328e139705a..14db75faccd 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -3207,3 +3207,4 @@
(include "generic.md")
(include "sifive-7.md")
(include "vector.md")
+(include "xventanacondops.md")
diff --git a/gcc/config/riscv/xventanacondops.md b/gcc/config/riscv/xventanacondops.md
new file mode 100644
index 00000000000..641cef0e44e
--- /dev/null
+++ b/gcc/config/riscv/xventanacondops.md
@@ -0,0 +1,30 @@
+;; Machine description for X-Ventana-CondOps
+;; Copyright (C) 2022 Free Software Foundation, Inc.
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3. If not see
+;; <http://www.gnu.org/licenses/>.
+
+(define_code_iterator eq_or_ne [eq ne])
+(define_code_attr n [(eq "n") (ne "")])
+
+(define_insn "*vt.maskc<n>"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (and:DI (neg:DI (eq_or_ne:DI
+ (match_operand:DI 1 "register_operand" "r")
+ (const_int 0)))
+ (match_operand:DI 2 "register_operand" "r")))]
+ "TARGET_XVENTANACONDOPS"
+ "vt.maskc<n>\t%0,%2,%1")
diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-03.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-03.c
new file mode 100644
index 00000000000..4a762a1ed61
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-03.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64 -mtune=thead-c906" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" "-Os" "-Oz" } } */
+
+long long ne3(long long a, long long b)
+{
+ if (a != 0)
+ return b;
+
+ return 0;
+}
+
+/* { dg-final { scan-assembler-times "vt.maskc" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-04.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-04.c
new file mode 100644
index 00000000000..18b35ac7070
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-04.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64 -mtune=thead-c906" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+
+long long ne4(long long a, long long b)
+{
+ if (a != 0)
+ return 0;
+
+ return b;
+}
+
+/* { dg-final { scan-assembler-times "vt.maskcn" 1 } } */
^ permalink raw reply [flat|nested] 6+ messages in thread
* [gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Generate vt.maskc<n> on noce_try_store_flag_mask if-conversion
@ 2022-11-18 20:22 Philipp Tomsich
0 siblings, 0 replies; 6+ messages in thread
From: Philipp Tomsich @ 2022-11-18 20:22 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:2967ccf7e8a3b6846a867065c475832aaf0680f2
commit 2967ccf7e8a3b6846a867065c475832aaf0680f2
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date: Sat Mar 5 23:21:10 2022 +0100
RISC-V: Generate vt.maskc<n> on noce_try_store_flag_mask if-conversion
Adds a pattern to map the output of noce_try_store_flag_mask
if-conversion in the combiner onto vt.maskc<n>; the input patterns
supported are similar to the following:
(set (reg/v/f:DI 75 [ <retval> ])
(and:DI (neg:DI (ne:DI (reg:DI 82)
(const_int 0 [0])))
(reg/v/f:DI 75 [ <retval> ])))
This reduces dynamic instruction counts for the perlbench-workload in
SPEC CPU2017 by 0.8230%, 0.4689%, and 0.2332% (respectively, for the
each of the 3 workloads in the 'ref'-workload).
To ensure that the combine-pass doesn't get confused about
profitability, we recognize the idiom as requiring a single
instruction when the XVentanaCondOps extension is present.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_rtx_costs): Recognize idiom for
vt.maskc<n> as a single insn with TARGET_XVENTANACONDOPS.
* config/riscv/riscv.md: Include xventanacondops.md.
* config/riscv/xventanacondops.md: New file.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/xventanacondops-ne-03.c: New test.
* gcc.target/riscv/xventanacondops-ne-04.c: New test.
Commit-changes: 2
- Ran whitespace-cleanup on xventanacondops-ne-03.c
- Ran whitespace-cleanup on xventanacondops-ne-04.c
Diff:
---
gcc/config/riscv/riscv.cc | 14 ++++++++++
gcc/config/riscv/riscv.md | 1 +
gcc/config/riscv/xventanacondops.md | 30 ++++++++++++++++++++++
.../gcc.target/riscv/xventanacondops-ne-03.c | 13 ++++++++++
.../gcc.target/riscv/xventanacondops-ne-04.c | 13 ++++++++++
5 files changed, 71 insertions(+)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 9a4dad40193..1e82b743c15 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -2307,6 +2307,20 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
return false;
case AND:
+ /* vt.maskc/vt.maskcn for XVentanaCondOps */
+ if (TARGET_XVENTANACONDOPS && mode == word_mode
+ && GET_CODE (XEXP (x, 0)) == NEG)
+ {
+ rtx inner = XEXP (XEXP (x, 0), 0);
+
+ if ((GET_CODE (inner) == EQ || GET_CODE (inner) == NE)
+ && CONST_INT_P (XEXP (inner, 1))
+ && INTVAL (XEXP (inner, 1)) == 0)
+ {
+ *total = COSTS_N_INSNS (1);
+ return true;
+ }
+ }
/* slli.uw pattern for zba. */
if (TARGET_ZBA && TARGET_64BIT && mode == DImode
&& GET_CODE (XEXP (x, 0)) == ASHIFT)
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 328e139705a..14db75faccd 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -3207,3 +3207,4 @@
(include "generic.md")
(include "sifive-7.md")
(include "vector.md")
+(include "xventanacondops.md")
diff --git a/gcc/config/riscv/xventanacondops.md b/gcc/config/riscv/xventanacondops.md
new file mode 100644
index 00000000000..641cef0e44e
--- /dev/null
+++ b/gcc/config/riscv/xventanacondops.md
@@ -0,0 +1,30 @@
+;; Machine description for X-Ventana-CondOps
+;; Copyright (C) 2022 Free Software Foundation, Inc.
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3. If not see
+;; <http://www.gnu.org/licenses/>.
+
+(define_code_iterator eq_or_ne [eq ne])
+(define_code_attr n [(eq "n") (ne "")])
+
+(define_insn "*vt.maskc<n>"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (and:DI (neg:DI (eq_or_ne:DI
+ (match_operand:DI 1 "register_operand" "r")
+ (const_int 0)))
+ (match_operand:DI 2 "register_operand" "r")))]
+ "TARGET_XVENTANACONDOPS"
+ "vt.maskc<n>\t%0,%2,%1")
diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-03.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-03.c
new file mode 100644
index 00000000000..4a762a1ed61
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-03.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64 -mtune=thead-c906" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" "-Os" "-Oz" } } */
+
+long long ne3(long long a, long long b)
+{
+ if (a != 0)
+ return b;
+
+ return 0;
+}
+
+/* { dg-final { scan-assembler-times "vt.maskc" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-04.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-04.c
new file mode 100644
index 00000000000..18b35ac7070
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-04.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64 -mtune=thead-c906" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+
+long long ne4(long long a, long long b)
+{
+ if (a != 0)
+ return 0;
+
+ return b;
+}
+
+/* { dg-final { scan-assembler-times "vt.maskcn" 1 } } */
^ permalink raw reply [flat|nested] 6+ messages in thread
* [gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Generate vt.maskc<n> on noce_try_store_flag_mask if-conversion
@ 2022-11-18 11:35 Philipp Tomsich
0 siblings, 0 replies; 6+ messages in thread
From: Philipp Tomsich @ 2022-11-18 11:35 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:9422ef42f2cebf069f907d05e65e78164d492547
commit 9422ef42f2cebf069f907d05e65e78164d492547
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date: Sat Mar 5 23:21:10 2022 +0100
RISC-V: Generate vt.maskc<n> on noce_try_store_flag_mask if-conversion
Adds a pattern to map the output of noce_try_store_flag_mask
if-conversion in the combiner onto vt.maskc<n>; the input patterns
supported are similar to the following:
(set (reg/v/f:DI 75 [ <retval> ])
(and:DI (neg:DI (ne:DI (reg:DI 82)
(const_int 0 [0])))
(reg/v/f:DI 75 [ <retval> ])))
This reduces dynamic instruction counts for the perlbench-workload in
SPEC CPU2017 by 0.8230%, 0.4689%, and 0.2332% (respectively, for the
each of the 3 workloads in the 'ref'-workload).
To ensure that the combine-pass doesn't get confused about
profitability, we recognize the idiom as requiring a single
instruction when the XVentanaCondOps extension is present.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_rtx_costs): Recognize idiom for
vt.maskc<n> as a single insn with TARGET_XVENTANACONDOPS.
* config/riscv/riscv.md: Include xventanacondops.md.
* config/riscv/xventanacondops.md: New file.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/xventanacondops-ne-03.c: New test.
* gcc.target/riscv/xventanacondops-ne-04.c: New test.
Commit-changes: 2
- Ran whitespace-cleanup on xventanacondops-ne-03.c
- Ran whitespace-cleanup on xventanacondops-ne-04.c
Diff:
---
gcc/config/riscv/riscv.cc | 14 ++++++++++
gcc/config/riscv/riscv.md | 1 +
gcc/config/riscv/xventanacondops.md | 30 ++++++++++++++++++++++
.../gcc.target/riscv/xventanacondops-ne-03.c | 13 ++++++++++
.../gcc.target/riscv/xventanacondops-ne-04.c | 13 ++++++++++
5 files changed, 71 insertions(+)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 56e6c7ff9a2..d34b1b7382a 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -2307,6 +2307,20 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
return false;
case AND:
+ /* vt.maskc/vt.maskcn for XVentanaCondOps */
+ if (TARGET_XVENTANACONDOPS && mode == word_mode
+ && GET_CODE (XEXP (x, 0)) == NEG)
+ {
+ rtx inner = XEXP (XEXP (x, 0), 0);
+
+ if ((GET_CODE (inner) == EQ || GET_CODE (inner) == NE)
+ && CONST_INT_P (XEXP (inner, 1))
+ && INTVAL (XEXP (inner, 1)) == 0)
+ {
+ *total = COSTS_N_INSNS (1);
+ return true;
+ }
+ }
/* slli.uw pattern for zba. */
if (TARGET_ZBA && TARGET_64BIT && mode == DImode
&& GET_CODE (XEXP (x, 0)) == ASHIFT)
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 328e139705a..14db75faccd 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -3207,3 +3207,4 @@
(include "generic.md")
(include "sifive-7.md")
(include "vector.md")
+(include "xventanacondops.md")
diff --git a/gcc/config/riscv/xventanacondops.md b/gcc/config/riscv/xventanacondops.md
new file mode 100644
index 00000000000..641cef0e44e
--- /dev/null
+++ b/gcc/config/riscv/xventanacondops.md
@@ -0,0 +1,30 @@
+;; Machine description for X-Ventana-CondOps
+;; Copyright (C) 2022 Free Software Foundation, Inc.
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3. If not see
+;; <http://www.gnu.org/licenses/>.
+
+(define_code_iterator eq_or_ne [eq ne])
+(define_code_attr n [(eq "n") (ne "")])
+
+(define_insn "*vt.maskc<n>"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (and:DI (neg:DI (eq_or_ne:DI
+ (match_operand:DI 1 "register_operand" "r")
+ (const_int 0)))
+ (match_operand:DI 2 "register_operand" "r")))]
+ "TARGET_XVENTANACONDOPS"
+ "vt.maskc<n>\t%0,%2,%1")
diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-03.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-03.c
new file mode 100644
index 00000000000..4a762a1ed61
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-03.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64 -mtune=thead-c906" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" "-Os" "-Oz" } } */
+
+long long ne3(long long a, long long b)
+{
+ if (a != 0)
+ return b;
+
+ return 0;
+}
+
+/* { dg-final { scan-assembler-times "vt.maskc" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-04.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-04.c
new file mode 100644
index 00000000000..18b35ac7070
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-04.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64 -mtune=thead-c906" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+
+long long ne4(long long a, long long b)
+{
+ if (a != 0)
+ return 0;
+
+ return b;
+}
+
+/* { dg-final { scan-assembler-times "vt.maskcn" 1 } } */
^ permalink raw reply [flat|nested] 6+ messages in thread
* [gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Generate vt.maskc<n> on noce_try_store_flag_mask if-conversion
@ 2022-11-17 22:26 Philipp Tomsich
0 siblings, 0 replies; 6+ messages in thread
From: Philipp Tomsich @ 2022-11-17 22:26 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:8187af43e1d87a9eada5f63db464643e1ad73f1a
commit 8187af43e1d87a9eada5f63db464643e1ad73f1a
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date: Sat Mar 5 23:21:10 2022 +0100
RISC-V: Generate vt.maskc<n> on noce_try_store_flag_mask if-conversion
Adds a pattern to map the output of noce_try_store_flag_mask
if-conversion in the combiner onto vt.maskc<n>; the input patterns
supported are similar to the following:
(set (reg/v/f:DI 75 [ <retval> ])
(and:DI (neg:DI (ne:DI (reg:DI 82)
(const_int 0 [0])))
(reg/v/f:DI 75 [ <retval> ])))
This reduces dynamic instruction counts for the perlbench-workload in
SPEC CPU2017 by 0.8230%, 0.4689%, and 0.2332% (respectively, for the
each of the 3 workloads in the 'ref'-workload).
To ensure that the combine-pass doesn't get confused about
profitability, we recognize the idiom as requiring a single
instruction when the XVentanaCondOps extension is present.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_rtx_costs): Recognize idiom for
vt.maskc<n> as a single insn with TARGET_XVENTANACONDOPS.
* config/riscv/riscv.md: Include xventanacondops.md.
* config/riscv/xventanacondops.md: New file.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/xventanacondops-ne-03.c: New test.
* gcc.target/riscv/xventanacondops-ne-04.c: New test.
Commit-changes: 2
- Ran whitespace-cleanup on xventanacondops-ne-03.c
- Ran whitespace-cleanup on xventanacondops-ne-04.c
Diff:
---
gcc/config/riscv/riscv.cc | 14 ++++++++++
gcc/config/riscv/riscv.md | 1 +
gcc/config/riscv/xventanacondops.md | 30 ++++++++++++++++++++++
.../gcc.target/riscv/xventanacondops-ne-03.c | 13 ++++++++++
.../gcc.target/riscv/xventanacondops-ne-04.c | 13 ++++++++++
5 files changed, 71 insertions(+)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 56e6c7ff9a2..d34b1b7382a 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -2307,6 +2307,20 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
return false;
case AND:
+ /* vt.maskc/vt.maskcn for XVentanaCondOps */
+ if (TARGET_XVENTANACONDOPS && mode == word_mode
+ && GET_CODE (XEXP (x, 0)) == NEG)
+ {
+ rtx inner = XEXP (XEXP (x, 0), 0);
+
+ if ((GET_CODE (inner) == EQ || GET_CODE (inner) == NE)
+ && CONST_INT_P (XEXP (inner, 1))
+ && INTVAL (XEXP (inner, 1)) == 0)
+ {
+ *total = COSTS_N_INSNS (1);
+ return true;
+ }
+ }
/* slli.uw pattern for zba. */
if (TARGET_ZBA && TARGET_64BIT && mode == DImode
&& GET_CODE (XEXP (x, 0)) == ASHIFT)
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 328e139705a..14db75faccd 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -3207,3 +3207,4 @@
(include "generic.md")
(include "sifive-7.md")
(include "vector.md")
+(include "xventanacondops.md")
diff --git a/gcc/config/riscv/xventanacondops.md b/gcc/config/riscv/xventanacondops.md
new file mode 100644
index 00000000000..641cef0e44e
--- /dev/null
+++ b/gcc/config/riscv/xventanacondops.md
@@ -0,0 +1,30 @@
+;; Machine description for X-Ventana-CondOps
+;; Copyright (C) 2022 Free Software Foundation, Inc.
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3. If not see
+;; <http://www.gnu.org/licenses/>.
+
+(define_code_iterator eq_or_ne [eq ne])
+(define_code_attr n [(eq "n") (ne "")])
+
+(define_insn "*vt.maskc<n>"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (and:DI (neg:DI (eq_or_ne:DI
+ (match_operand:DI 1 "register_operand" "r")
+ (const_int 0)))
+ (match_operand:DI 2 "register_operand" "r")))]
+ "TARGET_XVENTANACONDOPS"
+ "vt.maskc<n>\t%0,%2,%1")
diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-03.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-03.c
new file mode 100644
index 00000000000..4a762a1ed61
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-03.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64 -mtune=thead-c906" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" "-Os" "-Oz" } } */
+
+long long ne3(long long a, long long b)
+{
+ if (a != 0)
+ return b;
+
+ return 0;
+}
+
+/* { dg-final { scan-assembler-times "vt.maskc" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-04.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-04.c
new file mode 100644
index 00000000000..18b35ac7070
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-04.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64 -mtune=thead-c906" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+
+long long ne4(long long a, long long b)
+{
+ if (a != 0)
+ return 0;
+
+ return b;
+}
+
+/* { dg-final { scan-assembler-times "vt.maskcn" 1 } } */
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2022-12-01 13:23 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
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2022-11-17 22:26 Philipp Tomsich
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