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* [gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Recognize sign-extract + and cases for XVentanaCondOps
@ 2022-11-15 14:01 Philipp Tomsich
0 siblings, 0 replies; 7+ messages in thread
From: Philipp Tomsich @ 2022-11-15 14:01 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:3e365881b479c1622ceca74cc1be46e93c52c5cf
commit 3e365881b479c1622ceca74cc1be46e93c52c5cf
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date: Thu Mar 24 20:55:17 2022 +0100
RISC-V: Recognize sign-extract + and cases for XVentanaCondOps
Users might use explicit arithmetic operations to create a mask and
then and it, in a sequence like
cond = (bits >> SHIFT) & 1;
mask = ~(cond - 1);
val &= mask;
which will present as a single-bit sign-extract.
Dependening on what combination of XVentanaCondOps and Zbs are
available, this will map to the following sequences:
- bexti + vt.maskc, if both Zbs and XVentanaCondOps are present
- andi + vt.maskc, if only XVentanaCondOps is available and the
sign-extract is operating on bits 10:0 (bit
11 can't be reached, as the immediate is
sign-extended)
- slli + srli + and, otherwise.
gcc/ChangeLog:
* config/riscv/xventanacondops.md: Recognize SIGN_EXTRACT
of a single-bit followed by AND for XVentanaCondOps.
Diff:
---
gcc/config/riscv/xventanacondops.md | 45 ++++++++++++++++++++++
.../gcc.target/riscv/xventanacondops-le-01.c | 2 +-
.../gcc.target/riscv/xventanacondops-le-02.c | 11 ++++++
3 files changed, 57 insertions(+), 1 deletion(-)
diff --git a/gcc/config/riscv/xventanacondops.md b/gcc/config/riscv/xventanacondops.md
index 3d7427519b3..f2eb886659f 100644
--- a/gcc/config/riscv/xventanacondops.md
+++ b/gcc/config/riscv/xventanacondops.md
@@ -78,3 +78,48 @@
operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == LE ? GT : GTU,
<X:MODE>mode, operands[2], operands[3]);
})
+
+;; Users might use explicit arithmetic operations to create a mask and
+;; then and it, in a sequence like
+;; cond = (bits >> SHIFT) & 1;
+;; mask = ~(cond - 1);
+;; val &= mask;
+;; which will present as a single-bit sign-extract in the combiner.
+;;
+;; This will give rise to any of the following cases:
+;; - with Zbs and XVentanaCondOps: bexti + vt.maskc
+;; - with XVentanaCondOps (but w/o Zbs):
+;; - andi + vt.maskc, if the mask is representable in the immediate
+;; (which requires extra care due to the immediate
+;; being sign-extended)
+;; - slli + srli + and
+;; - otherwise: slli + srli + and
+
+;; With Zbb, we have bexti for all possible bits...
+(define_split
+ [(set (match_operand:X 0 "register_operand")
+ (and:X (sign_extract:X (match_operand:X 1 "register_operand")
+ (const_int 1)
+ (match_operand 2 "immediate_operand"))
+ (match_operand:X 3 "register_operand")))
+ (clobber (match_operand:X 4 "register_operand"))]
+ "TARGET_XVENTANACONDOPS && TARGET_ZBS"
+ [(set (match_dup 4) (zero_extract:X (match_dup 1) (const_int 1) (match_dup 2)))
+ (set (match_dup 0) (and:X (neg:X (ne:X (match_dup 4) (const_int 0)))
+ (match_dup 3)))])
+
+;; ...whereas RV64I only allows us access to bits 0..10 in a single andi.
+(define_split
+ [(set (match_operand:X 0 "register_operand")
+ (and:X (sign_extract:X (match_operand:X 1 "register_operand")
+ (const_int 1)
+ (match_operand 2 "immediate_operand"))
+ (match_operand:X 3 "register_operand")))
+ (clobber (match_operand:X 4 "register_operand"))]
+ "TARGET_XVENTANACONDOPS && !TARGET_ZBS && (UINTVAL (operands[2]) < 11)"
+ [(set (match_dup 4) (and:X (match_dup 1) (match_dup 2)))
+ (set (match_dup 0) (and:X (neg:X (ne:X (match_dup 4) (const_int 0)))
+ (match_dup 3)))]
+{
+ operands[2] = GEN_INT(1 << UINTVAL(operands[2]));
+})
diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-le-01.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-le-01.c
index f6f80958e9d..eb463e3c161 100644
--- a/gcc/testsuite/gcc.target/riscv/xventanacondops-le-01.c
+++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-le-01.c
@@ -4,7 +4,7 @@
long long sink (long long);
-long long lt3 (long long a, long long b)
+long long le1 (long long a, long long b)
{
if (a <= b)
b = 0;
diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-le-02.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-le-02.c
new file mode 100644
index 00000000000..da074436f40
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-le-02.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zba_zbb_zbs_xventanacondops -mabi=lp64 -mbranch-cost=4" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" "-Os" "-Oz" } } */
+
+long long le2 (long long a, long long b, long long c)
+{
+ return (a <= c) ? b : 0;
+}
+
+/* { dg-final { scan-assembler-times "sgt\t" 1 } } */
+/* { dg-final { scan-assembler-times "vt.maskc\t" 1 } } */
^ permalink raw reply [flat|nested] 7+ messages in thread
* [gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Recognize sign-extract + and cases for XVentanaCondOps
@ 2022-12-01 13:23 Philipp Tomsich
0 siblings, 0 replies; 7+ messages in thread
From: Philipp Tomsich @ 2022-12-01 13:23 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:029a73afbcacac6e0d4f7b330d78b3d38d9b3d43
commit 029a73afbcacac6e0d4f7b330d78b3d38d9b3d43
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date: Thu Mar 24 20:55:17 2022 +0100
RISC-V: Recognize sign-extract + and cases for XVentanaCondOps
Users might use explicit arithmetic operations to create a mask and
then and it, in a sequence like
cond = (bits >> SHIFT) & 1;
mask = ~(cond - 1);
val &= mask;
which will present as a single-bit sign-extract.
Dependening on what combination of XVentanaCondOps and Zbs are
available, this will map to the following sequences:
- bexti + vt.maskc, if both Zbs and XVentanaCondOps are present
- andi + vt.maskc, if only XVentanaCondOps is available and the
sign-extract is operating on bits 10:0 (bit
11 can't be reached, as the immediate is
sign-extended)
- slli + srli + and, otherwise.
gcc/ChangeLog:
* config/riscv/xventanacondops.md: Recognize SIGN_EXTRACT
of a single-bit followed by AND for XVentanaCondOps.
Diff:
---
gcc/config/riscv/xventanacondops.md | 45 ++++++++++++++++++++++
.../gcc.target/riscv/xventanacondops-le-01.c | 2 +-
2 files changed, 46 insertions(+), 1 deletion(-)
diff --git a/gcc/config/riscv/xventanacondops.md b/gcc/config/riscv/xventanacondops.md
index 3d7427519b3..f2eb886659f 100644
--- a/gcc/config/riscv/xventanacondops.md
+++ b/gcc/config/riscv/xventanacondops.md
@@ -78,3 +78,48 @@
operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == LE ? GT : GTU,
<X:MODE>mode, operands[2], operands[3]);
})
+
+;; Users might use explicit arithmetic operations to create a mask and
+;; then and it, in a sequence like
+;; cond = (bits >> SHIFT) & 1;
+;; mask = ~(cond - 1);
+;; val &= mask;
+;; which will present as a single-bit sign-extract in the combiner.
+;;
+;; This will give rise to any of the following cases:
+;; - with Zbs and XVentanaCondOps: bexti + vt.maskc
+;; - with XVentanaCondOps (but w/o Zbs):
+;; - andi + vt.maskc, if the mask is representable in the immediate
+;; (which requires extra care due to the immediate
+;; being sign-extended)
+;; - slli + srli + and
+;; - otherwise: slli + srli + and
+
+;; With Zbb, we have bexti for all possible bits...
+(define_split
+ [(set (match_operand:X 0 "register_operand")
+ (and:X (sign_extract:X (match_operand:X 1 "register_operand")
+ (const_int 1)
+ (match_operand 2 "immediate_operand"))
+ (match_operand:X 3 "register_operand")))
+ (clobber (match_operand:X 4 "register_operand"))]
+ "TARGET_XVENTANACONDOPS && TARGET_ZBS"
+ [(set (match_dup 4) (zero_extract:X (match_dup 1) (const_int 1) (match_dup 2)))
+ (set (match_dup 0) (and:X (neg:X (ne:X (match_dup 4) (const_int 0)))
+ (match_dup 3)))])
+
+;; ...whereas RV64I only allows us access to bits 0..10 in a single andi.
+(define_split
+ [(set (match_operand:X 0 "register_operand")
+ (and:X (sign_extract:X (match_operand:X 1 "register_operand")
+ (const_int 1)
+ (match_operand 2 "immediate_operand"))
+ (match_operand:X 3 "register_operand")))
+ (clobber (match_operand:X 4 "register_operand"))]
+ "TARGET_XVENTANACONDOPS && !TARGET_ZBS && (UINTVAL (operands[2]) < 11)"
+ [(set (match_dup 4) (and:X (match_dup 1) (match_dup 2)))
+ (set (match_dup 0) (and:X (neg:X (ne:X (match_dup 4) (const_int 0)))
+ (match_dup 3)))]
+{
+ operands[2] = GEN_INT(1 << UINTVAL(operands[2]));
+})
diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-le-01.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-le-01.c
index f6f80958e9d..eb463e3c161 100644
--- a/gcc/testsuite/gcc.target/riscv/xventanacondops-le-01.c
+++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-le-01.c
@@ -4,7 +4,7 @@
long long sink (long long);
-long long lt3 (long long a, long long b)
+long long le1 (long long a, long long b)
{
if (a <= b)
b = 0;
^ permalink raw reply [flat|nested] 7+ messages in thread
* [gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Recognize sign-extract + and cases for XVentanaCondOps
@ 2022-11-18 20:25 Philipp Tomsich
0 siblings, 0 replies; 7+ messages in thread
From: Philipp Tomsich @ 2022-11-18 20:25 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:95fbae489fa57652b7037239d66bf21b737801ee
commit 95fbae489fa57652b7037239d66bf21b737801ee
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date: Thu Mar 24 20:55:17 2022 +0100
RISC-V: Recognize sign-extract + and cases for XVentanaCondOps
Users might use explicit arithmetic operations to create a mask and
then and it, in a sequence like
cond = (bits >> SHIFT) & 1;
mask = ~(cond - 1);
val &= mask;
which will present as a single-bit sign-extract.
Dependening on what combination of XVentanaCondOps and Zbs are
available, this will map to the following sequences:
- bexti + vt.maskc, if both Zbs and XVentanaCondOps are present
- andi + vt.maskc, if only XVentanaCondOps is available and the
sign-extract is operating on bits 10:0 (bit
11 can't be reached, as the immediate is
sign-extended)
- slli + srli + and, otherwise.
gcc/ChangeLog:
* config/riscv/xventanacondops.md: Recognize SIGN_EXTRACT
of a single-bit followed by AND for XVentanaCondOps.
Diff:
---
gcc/config/riscv/xventanacondops.md | 45 ++++++++++++++++++++++
.../gcc.target/riscv/xventanacondops-le-01.c | 2 +-
2 files changed, 46 insertions(+), 1 deletion(-)
diff --git a/gcc/config/riscv/xventanacondops.md b/gcc/config/riscv/xventanacondops.md
index 3d7427519b3..f2eb886659f 100644
--- a/gcc/config/riscv/xventanacondops.md
+++ b/gcc/config/riscv/xventanacondops.md
@@ -78,3 +78,48 @@
operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == LE ? GT : GTU,
<X:MODE>mode, operands[2], operands[3]);
})
+
+;; Users might use explicit arithmetic operations to create a mask and
+;; then and it, in a sequence like
+;; cond = (bits >> SHIFT) & 1;
+;; mask = ~(cond - 1);
+;; val &= mask;
+;; which will present as a single-bit sign-extract in the combiner.
+;;
+;; This will give rise to any of the following cases:
+;; - with Zbs and XVentanaCondOps: bexti + vt.maskc
+;; - with XVentanaCondOps (but w/o Zbs):
+;; - andi + vt.maskc, if the mask is representable in the immediate
+;; (which requires extra care due to the immediate
+;; being sign-extended)
+;; - slli + srli + and
+;; - otherwise: slli + srli + and
+
+;; With Zbb, we have bexti for all possible bits...
+(define_split
+ [(set (match_operand:X 0 "register_operand")
+ (and:X (sign_extract:X (match_operand:X 1 "register_operand")
+ (const_int 1)
+ (match_operand 2 "immediate_operand"))
+ (match_operand:X 3 "register_operand")))
+ (clobber (match_operand:X 4 "register_operand"))]
+ "TARGET_XVENTANACONDOPS && TARGET_ZBS"
+ [(set (match_dup 4) (zero_extract:X (match_dup 1) (const_int 1) (match_dup 2)))
+ (set (match_dup 0) (and:X (neg:X (ne:X (match_dup 4) (const_int 0)))
+ (match_dup 3)))])
+
+;; ...whereas RV64I only allows us access to bits 0..10 in a single andi.
+(define_split
+ [(set (match_operand:X 0 "register_operand")
+ (and:X (sign_extract:X (match_operand:X 1 "register_operand")
+ (const_int 1)
+ (match_operand 2 "immediate_operand"))
+ (match_operand:X 3 "register_operand")))
+ (clobber (match_operand:X 4 "register_operand"))]
+ "TARGET_XVENTANACONDOPS && !TARGET_ZBS && (UINTVAL (operands[2]) < 11)"
+ [(set (match_dup 4) (and:X (match_dup 1) (match_dup 2)))
+ (set (match_dup 0) (and:X (neg:X (ne:X (match_dup 4) (const_int 0)))
+ (match_dup 3)))]
+{
+ operands[2] = GEN_INT(1 << UINTVAL(operands[2]));
+})
diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-le-01.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-le-01.c
index f6f80958e9d..eb463e3c161 100644
--- a/gcc/testsuite/gcc.target/riscv/xventanacondops-le-01.c
+++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-le-01.c
@@ -4,7 +4,7 @@
long long sink (long long);
-long long lt3 (long long a, long long b)
+long long le1 (long long a, long long b)
{
if (a <= b)
b = 0;
^ permalink raw reply [flat|nested] 7+ messages in thread
* [gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Recognize sign-extract + and cases for XVentanaCondOps
@ 2022-11-18 20:22 Philipp Tomsich
0 siblings, 0 replies; 7+ messages in thread
From: Philipp Tomsich @ 2022-11-18 20:22 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:9bedb1c5b9467ba90f33335393d9ee4432cef323
commit 9bedb1c5b9467ba90f33335393d9ee4432cef323
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date: Thu Mar 24 20:55:17 2022 +0100
RISC-V: Recognize sign-extract + and cases for XVentanaCondOps
Users might use explicit arithmetic operations to create a mask and
then and it, in a sequence like
cond = (bits >> SHIFT) & 1;
mask = ~(cond - 1);
val &= mask;
which will present as a single-bit sign-extract.
Dependening on what combination of XVentanaCondOps and Zbs are
available, this will map to the following sequences:
- bexti + vt.maskc, if both Zbs and XVentanaCondOps are present
- andi + vt.maskc, if only XVentanaCondOps is available and the
sign-extract is operating on bits 10:0 (bit
11 can't be reached, as the immediate is
sign-extended)
- slli + srli + and, otherwise.
gcc/ChangeLog:
* config/riscv/xventanacondops.md: Recognize SIGN_EXTRACT
of a single-bit followed by AND for XVentanaCondOps.
Diff:
---
gcc/config/riscv/xventanacondops.md | 45 ++++++++++++++++++++++
.../gcc.target/riscv/xventanacondops-le-01.c | 2 +-
2 files changed, 46 insertions(+), 1 deletion(-)
diff --git a/gcc/config/riscv/xventanacondops.md b/gcc/config/riscv/xventanacondops.md
index 3d7427519b3..f2eb886659f 100644
--- a/gcc/config/riscv/xventanacondops.md
+++ b/gcc/config/riscv/xventanacondops.md
@@ -78,3 +78,48 @@
operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == LE ? GT : GTU,
<X:MODE>mode, operands[2], operands[3]);
})
+
+;; Users might use explicit arithmetic operations to create a mask and
+;; then and it, in a sequence like
+;; cond = (bits >> SHIFT) & 1;
+;; mask = ~(cond - 1);
+;; val &= mask;
+;; which will present as a single-bit sign-extract in the combiner.
+;;
+;; This will give rise to any of the following cases:
+;; - with Zbs and XVentanaCondOps: bexti + vt.maskc
+;; - with XVentanaCondOps (but w/o Zbs):
+;; - andi + vt.maskc, if the mask is representable in the immediate
+;; (which requires extra care due to the immediate
+;; being sign-extended)
+;; - slli + srli + and
+;; - otherwise: slli + srli + and
+
+;; With Zbb, we have bexti for all possible bits...
+(define_split
+ [(set (match_operand:X 0 "register_operand")
+ (and:X (sign_extract:X (match_operand:X 1 "register_operand")
+ (const_int 1)
+ (match_operand 2 "immediate_operand"))
+ (match_operand:X 3 "register_operand")))
+ (clobber (match_operand:X 4 "register_operand"))]
+ "TARGET_XVENTANACONDOPS && TARGET_ZBS"
+ [(set (match_dup 4) (zero_extract:X (match_dup 1) (const_int 1) (match_dup 2)))
+ (set (match_dup 0) (and:X (neg:X (ne:X (match_dup 4) (const_int 0)))
+ (match_dup 3)))])
+
+;; ...whereas RV64I only allows us access to bits 0..10 in a single andi.
+(define_split
+ [(set (match_operand:X 0 "register_operand")
+ (and:X (sign_extract:X (match_operand:X 1 "register_operand")
+ (const_int 1)
+ (match_operand 2 "immediate_operand"))
+ (match_operand:X 3 "register_operand")))
+ (clobber (match_operand:X 4 "register_operand"))]
+ "TARGET_XVENTANACONDOPS && !TARGET_ZBS && (UINTVAL (operands[2]) < 11)"
+ [(set (match_dup 4) (and:X (match_dup 1) (match_dup 2)))
+ (set (match_dup 0) (and:X (neg:X (ne:X (match_dup 4) (const_int 0)))
+ (match_dup 3)))]
+{
+ operands[2] = GEN_INT(1 << UINTVAL(operands[2]));
+})
diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-le-01.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-le-01.c
index f6f80958e9d..eb463e3c161 100644
--- a/gcc/testsuite/gcc.target/riscv/xventanacondops-le-01.c
+++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-le-01.c
@@ -4,7 +4,7 @@
long long sink (long long);
-long long lt3 (long long a, long long b)
+long long le1 (long long a, long long b)
{
if (a <= b)
b = 0;
^ permalink raw reply [flat|nested] 7+ messages in thread
* [gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Recognize sign-extract + and cases for XVentanaCondOps
@ 2022-11-18 11:35 Philipp Tomsich
0 siblings, 0 replies; 7+ messages in thread
From: Philipp Tomsich @ 2022-11-18 11:35 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:92ef98367bc7c316a45aed511b6c89c705221274
commit 92ef98367bc7c316a45aed511b6c89c705221274
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date: Thu Mar 24 20:55:17 2022 +0100
RISC-V: Recognize sign-extract + and cases for XVentanaCondOps
Users might use explicit arithmetic operations to create a mask and
then and it, in a sequence like
cond = (bits >> SHIFT) & 1;
mask = ~(cond - 1);
val &= mask;
which will present as a single-bit sign-extract.
Dependening on what combination of XVentanaCondOps and Zbs are
available, this will map to the following sequences:
- bexti + vt.maskc, if both Zbs and XVentanaCondOps are present
- andi + vt.maskc, if only XVentanaCondOps is available and the
sign-extract is operating on bits 10:0 (bit
11 can't be reached, as the immediate is
sign-extended)
- slli + srli + and, otherwise.
gcc/ChangeLog:
* config/riscv/xventanacondops.md: Recognize SIGN_EXTRACT
of a single-bit followed by AND for XVentanaCondOps.
Diff:
---
gcc/config/riscv/xventanacondops.md | 45 ++++++++++++++++++++++
.../gcc.target/riscv/xventanacondops-le-01.c | 2 +-
2 files changed, 46 insertions(+), 1 deletion(-)
diff --git a/gcc/config/riscv/xventanacondops.md b/gcc/config/riscv/xventanacondops.md
index 3d7427519b3..f2eb886659f 100644
--- a/gcc/config/riscv/xventanacondops.md
+++ b/gcc/config/riscv/xventanacondops.md
@@ -78,3 +78,48 @@
operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == LE ? GT : GTU,
<X:MODE>mode, operands[2], operands[3]);
})
+
+;; Users might use explicit arithmetic operations to create a mask and
+;; then and it, in a sequence like
+;; cond = (bits >> SHIFT) & 1;
+;; mask = ~(cond - 1);
+;; val &= mask;
+;; which will present as a single-bit sign-extract in the combiner.
+;;
+;; This will give rise to any of the following cases:
+;; - with Zbs and XVentanaCondOps: bexti + vt.maskc
+;; - with XVentanaCondOps (but w/o Zbs):
+;; - andi + vt.maskc, if the mask is representable in the immediate
+;; (which requires extra care due to the immediate
+;; being sign-extended)
+;; - slli + srli + and
+;; - otherwise: slli + srli + and
+
+;; With Zbb, we have bexti for all possible bits...
+(define_split
+ [(set (match_operand:X 0 "register_operand")
+ (and:X (sign_extract:X (match_operand:X 1 "register_operand")
+ (const_int 1)
+ (match_operand 2 "immediate_operand"))
+ (match_operand:X 3 "register_operand")))
+ (clobber (match_operand:X 4 "register_operand"))]
+ "TARGET_XVENTANACONDOPS && TARGET_ZBS"
+ [(set (match_dup 4) (zero_extract:X (match_dup 1) (const_int 1) (match_dup 2)))
+ (set (match_dup 0) (and:X (neg:X (ne:X (match_dup 4) (const_int 0)))
+ (match_dup 3)))])
+
+;; ...whereas RV64I only allows us access to bits 0..10 in a single andi.
+(define_split
+ [(set (match_operand:X 0 "register_operand")
+ (and:X (sign_extract:X (match_operand:X 1 "register_operand")
+ (const_int 1)
+ (match_operand 2 "immediate_operand"))
+ (match_operand:X 3 "register_operand")))
+ (clobber (match_operand:X 4 "register_operand"))]
+ "TARGET_XVENTANACONDOPS && !TARGET_ZBS && (UINTVAL (operands[2]) < 11)"
+ [(set (match_dup 4) (and:X (match_dup 1) (match_dup 2)))
+ (set (match_dup 0) (and:X (neg:X (ne:X (match_dup 4) (const_int 0)))
+ (match_dup 3)))]
+{
+ operands[2] = GEN_INT(1 << UINTVAL(operands[2]));
+})
diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-le-01.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-le-01.c
index f6f80958e9d..eb463e3c161 100644
--- a/gcc/testsuite/gcc.target/riscv/xventanacondops-le-01.c
+++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-le-01.c
@@ -4,7 +4,7 @@
long long sink (long long);
-long long lt3 (long long a, long long b)
+long long le1 (long long a, long long b)
{
if (a <= b)
b = 0;
^ permalink raw reply [flat|nested] 7+ messages in thread
* [gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Recognize sign-extract + and cases for XVentanaCondOps
@ 2022-11-17 22:26 Philipp Tomsich
0 siblings, 0 replies; 7+ messages in thread
From: Philipp Tomsich @ 2022-11-17 22:26 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:f1cb12c4b880008d0de554384f68c4833bc74289
commit f1cb12c4b880008d0de554384f68c4833bc74289
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date: Thu Mar 24 20:55:17 2022 +0100
RISC-V: Recognize sign-extract + and cases for XVentanaCondOps
Users might use explicit arithmetic operations to create a mask and
then and it, in a sequence like
cond = (bits >> SHIFT) & 1;
mask = ~(cond - 1);
val &= mask;
which will present as a single-bit sign-extract.
Dependening on what combination of XVentanaCondOps and Zbs are
available, this will map to the following sequences:
- bexti + vt.maskc, if both Zbs and XVentanaCondOps are present
- andi + vt.maskc, if only XVentanaCondOps is available and the
sign-extract is operating on bits 10:0 (bit
11 can't be reached, as the immediate is
sign-extended)
- slli + srli + and, otherwise.
gcc/ChangeLog:
* config/riscv/xventanacondops.md: Recognize SIGN_EXTRACT
of a single-bit followed by AND for XVentanaCondOps.
Diff:
---
gcc/config/riscv/xventanacondops.md | 45 ++++++++++++++++++++++
.../gcc.target/riscv/xventanacondops-le-01.c | 2 +-
2 files changed, 46 insertions(+), 1 deletion(-)
diff --git a/gcc/config/riscv/xventanacondops.md b/gcc/config/riscv/xventanacondops.md
index 3d7427519b3..f2eb886659f 100644
--- a/gcc/config/riscv/xventanacondops.md
+++ b/gcc/config/riscv/xventanacondops.md
@@ -78,3 +78,48 @@
operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == LE ? GT : GTU,
<X:MODE>mode, operands[2], operands[3]);
})
+
+;; Users might use explicit arithmetic operations to create a mask and
+;; then and it, in a sequence like
+;; cond = (bits >> SHIFT) & 1;
+;; mask = ~(cond - 1);
+;; val &= mask;
+;; which will present as a single-bit sign-extract in the combiner.
+;;
+;; This will give rise to any of the following cases:
+;; - with Zbs and XVentanaCondOps: bexti + vt.maskc
+;; - with XVentanaCondOps (but w/o Zbs):
+;; - andi + vt.maskc, if the mask is representable in the immediate
+;; (which requires extra care due to the immediate
+;; being sign-extended)
+;; - slli + srli + and
+;; - otherwise: slli + srli + and
+
+;; With Zbb, we have bexti for all possible bits...
+(define_split
+ [(set (match_operand:X 0 "register_operand")
+ (and:X (sign_extract:X (match_operand:X 1 "register_operand")
+ (const_int 1)
+ (match_operand 2 "immediate_operand"))
+ (match_operand:X 3 "register_operand")))
+ (clobber (match_operand:X 4 "register_operand"))]
+ "TARGET_XVENTANACONDOPS && TARGET_ZBS"
+ [(set (match_dup 4) (zero_extract:X (match_dup 1) (const_int 1) (match_dup 2)))
+ (set (match_dup 0) (and:X (neg:X (ne:X (match_dup 4) (const_int 0)))
+ (match_dup 3)))])
+
+;; ...whereas RV64I only allows us access to bits 0..10 in a single andi.
+(define_split
+ [(set (match_operand:X 0 "register_operand")
+ (and:X (sign_extract:X (match_operand:X 1 "register_operand")
+ (const_int 1)
+ (match_operand 2 "immediate_operand"))
+ (match_operand:X 3 "register_operand")))
+ (clobber (match_operand:X 4 "register_operand"))]
+ "TARGET_XVENTANACONDOPS && !TARGET_ZBS && (UINTVAL (operands[2]) < 11)"
+ [(set (match_dup 4) (and:X (match_dup 1) (match_dup 2)))
+ (set (match_dup 0) (and:X (neg:X (ne:X (match_dup 4) (const_int 0)))
+ (match_dup 3)))]
+{
+ operands[2] = GEN_INT(1 << UINTVAL(operands[2]));
+})
diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-le-01.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-le-01.c
index f6f80958e9d..eb463e3c161 100644
--- a/gcc/testsuite/gcc.target/riscv/xventanacondops-le-01.c
+++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-le-01.c
@@ -4,7 +4,7 @@
long long sink (long long);
-long long lt3 (long long a, long long b)
+long long le1 (long long a, long long b)
{
if (a <= b)
b = 0;
^ permalink raw reply [flat|nested] 7+ messages in thread
* [gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Recognize sign-extract + and cases for XVentanaCondOps
@ 2022-11-15 14:59 Philipp Tomsich
0 siblings, 0 replies; 7+ messages in thread
From: Philipp Tomsich @ 2022-11-15 14:59 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:442eed78b4bd08bb3a6e8a27a9ef33b433f437b1
commit 442eed78b4bd08bb3a6e8a27a9ef33b433f437b1
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date: Thu Mar 24 20:55:17 2022 +0100
RISC-V: Recognize sign-extract + and cases for XVentanaCondOps
Users might use explicit arithmetic operations to create a mask and
then and it, in a sequence like
cond = (bits >> SHIFT) & 1;
mask = ~(cond - 1);
val &= mask;
which will present as a single-bit sign-extract.
Dependening on what combination of XVentanaCondOps and Zbs are
available, this will map to the following sequences:
- bexti + vt.maskc, if both Zbs and XVentanaCondOps are present
- andi + vt.maskc, if only XVentanaCondOps is available and the
sign-extract is operating on bits 10:0 (bit
11 can't be reached, as the immediate is
sign-extended)
- slli + srli + and, otherwise.
gcc/ChangeLog:
* config/riscv/xventanacondops.md: Recognize SIGN_EXTRACT
of a single-bit followed by AND for XVentanaCondOps.
Diff:
---
gcc/config/riscv/xventanacondops.md | 45 ++++++++++++++++++++++
.../gcc.target/riscv/xventanacondops-le-01.c | 2 +-
2 files changed, 46 insertions(+), 1 deletion(-)
diff --git a/gcc/config/riscv/xventanacondops.md b/gcc/config/riscv/xventanacondops.md
index 3d7427519b3e..f2eb886659fe 100644
--- a/gcc/config/riscv/xventanacondops.md
+++ b/gcc/config/riscv/xventanacondops.md
@@ -78,3 +78,48 @@
operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == LE ? GT : GTU,
<X:MODE>mode, operands[2], operands[3]);
})
+
+;; Users might use explicit arithmetic operations to create a mask and
+;; then and it, in a sequence like
+;; cond = (bits >> SHIFT) & 1;
+;; mask = ~(cond - 1);
+;; val &= mask;
+;; which will present as a single-bit sign-extract in the combiner.
+;;
+;; This will give rise to any of the following cases:
+;; - with Zbs and XVentanaCondOps: bexti + vt.maskc
+;; - with XVentanaCondOps (but w/o Zbs):
+;; - andi + vt.maskc, if the mask is representable in the immediate
+;; (which requires extra care due to the immediate
+;; being sign-extended)
+;; - slli + srli + and
+;; - otherwise: slli + srli + and
+
+;; With Zbb, we have bexti for all possible bits...
+(define_split
+ [(set (match_operand:X 0 "register_operand")
+ (and:X (sign_extract:X (match_operand:X 1 "register_operand")
+ (const_int 1)
+ (match_operand 2 "immediate_operand"))
+ (match_operand:X 3 "register_operand")))
+ (clobber (match_operand:X 4 "register_operand"))]
+ "TARGET_XVENTANACONDOPS && TARGET_ZBS"
+ [(set (match_dup 4) (zero_extract:X (match_dup 1) (const_int 1) (match_dup 2)))
+ (set (match_dup 0) (and:X (neg:X (ne:X (match_dup 4) (const_int 0)))
+ (match_dup 3)))])
+
+;; ...whereas RV64I only allows us access to bits 0..10 in a single andi.
+(define_split
+ [(set (match_operand:X 0 "register_operand")
+ (and:X (sign_extract:X (match_operand:X 1 "register_operand")
+ (const_int 1)
+ (match_operand 2 "immediate_operand"))
+ (match_operand:X 3 "register_operand")))
+ (clobber (match_operand:X 4 "register_operand"))]
+ "TARGET_XVENTANACONDOPS && !TARGET_ZBS && (UINTVAL (operands[2]) < 11)"
+ [(set (match_dup 4) (and:X (match_dup 1) (match_dup 2)))
+ (set (match_dup 0) (and:X (neg:X (ne:X (match_dup 4) (const_int 0)))
+ (match_dup 3)))]
+{
+ operands[2] = GEN_INT(1 << UINTVAL(operands[2]));
+})
diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-le-01.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-le-01.c
index f6f80958e9dd..eb463e3c161c 100644
--- a/gcc/testsuite/gcc.target/riscv/xventanacondops-le-01.c
+++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-le-01.c
@@ -4,7 +4,7 @@
long long sink (long long);
-long long lt3 (long long a, long long b)
+long long le1 (long long a, long long b)
{
if (a <= b)
b = 0;
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2022-12-01 13:23 UTC | newest]
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